Technical Webinar Series: 1July

 

IMAPS Live Technical Webinar Series 

 

CHIP-TO-CHIP INTEGRATION FOR HIGH BANDWIDTH MEMORY PROCESSOR INTERFACE

Speaker Andy Heinig, Fraunhofer IIS


Wednesday, July 1, 2020 | 12:00pm – 12:45pm EASTERN | Webex

 

Most electronic systems comprise a processing unit and some memory as basis components. Devices with a high compute power also demand a lot of embedded memory. In many cases this embedded memory is integrated within the same IC. This is maybe not the best solution for each case, since processing unit and embedded memory  have different requirements. So a technology could be optimized for performance or memory but not both. Also the demand for metal stack is distinct. Processing units need a lot of metal layers for proper routing and memory typically comes out with a lot less, because of the regular arrangement. Because of these differences it can be suitable to divide processing and memory during production and merge both during assembly. In this webinar, the idea to partitioning processing and memory is presented and an example low-cost chip stack-up will be described, that is currently in production.



Speaker: Andy Heinig

Andy Heinig has been working at Fraunhofer since 2007. Currently, he is the head of the department efficient electronics. In this position, he leads national and international research projects in the field of advanced packaging and 2.5, 3D-integrated circuits. His research interests concern layout automation for 2.5/3D-integration of circuits, algorithms for pathfinding in 3D-systems and modelling of physical effects in the range of advanced packaging. Moreover, he acts as person responsible in different standardization organizations, e.g. the Si2 working group Chip-package-codesign.








Registration Details:
Registration is FREE for IMAPS members, including student members.
Non-member registration is $50.

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This webinar will be hosted via Webex. Registrants will receive an email prior to the start of the webinar with login instructions.