Exhibition         
October 12 - 13, 2021

 On Demand

Program 

Course A1: System-in-Package (SiP) - System Solutions Through Miniaturization -Instructor: Mark Gerber, ASE US, Inc.

ROOM: PALM 1

This PDC course will introduce the package platform SiP (System-in-Package) and how some companies are diversifying from SOC (System-on-a-Chip) to leverage heterogeneous silicon integration and package miniaturization to enable system level solutions. A short market perspective will be reviewed as well as how industry segments are leveraging SiP and how the OEM market is evolving and creating system level ecosystems to enabling content revenue- a key area of IOT. SiP general process flow details will be covered as well as key process considerations for yield improvements. In addition, a brief overview of some of the tools that may be leveraged to help miniaturize module solutions and improve performance. This class will also introduce several variations of the SIP platform using Fan-Out Wafer Level packaging and new embedded substrate technologies are also emerging as powerful future platforms to enable lower power and higher performance devices using solderless interconnects.

Course A2 (VIRTUAL LIVESTREAM ONLY): Packaging Technologies and Antenna-in-Package Solutions for 5G Applications - Instructors: Ivan Ndip and Markus Woehrmann, Fraunhofer IZM 

ROOM: PALM 2

5G has been rolled-out in many parts of the world. Although the on-going commercialization focuses on 5G sub-6 GHz systems (i.e., 5G systems which operate below 6GHz), some 5G millimeter-wave (mmWave) products are expected in market this year. Unlike 5G sub-6 GHz, 5G mmWave systems operate in the 24-29 GHz and 37-40 GHz bands. These system are expected to enable peak data rates of about 20 Gbps and latency of approximately 1 millisecond. Such high data rates and low latency, combined with novel artificial intelligence techniques, will enable new applications that would transform our lives, economy and society.
Electronic packaging plays a key role in the development of 5G mmWave systems. It enables the fabrication and integration of 5G mmWave antennas and passive components, the development of antenna-in-package (AiP) frontend modules and the assembly of AiP frontend modules on system-boards with integrated baseband and signal processing circuits.
The main objective of this course is to present and extensively discuss different advanced packaging technologies and AiP solutions for 5G mmWave applications.
The course is structured in five sections. In the first section, worldwide allocation of 5G frequency spectrum and applications of 5G mmWave will be presented. This will be followed a presentation of the challenges of 5G mobile communication at mmWave frequencies and possible solutions using MIMO (Multiple Input Multiple Output) and beamforming system architectures. In the second section, an elaborate discussion of the packaging requirements and challenges for hardware implementation of 5G mmWave system architectures will be presented. The third section focuses on in-depth analysis and evaluation of AiP solutions with respect to the packaging requirements. In the fourth section, an extensive discussion of advanced packaging technologies, materials and processes used for the fabrication of 5G mmWave systems will be presented. Finally, in section five, examples of 5G mmWave package integrated antenna arrays, designed and fabricated using these advanced packaging technologies will be presented. Techniques for measurement-based extraction of the relative dielectric constant and loss tangent of packaging materials for 5G mm Wave applications will also be presented in this section.

CANCELED -- Course A3 (VIRTUAL LIVESTREAM ONLY): Achieving High Reliability Leadfree Solder Joints - Materials Consideration - Instructor: Ning-Cheng Lee, Consultant

PDC Coffee Break in Foyer

Course B1: Advances in Fan-Out Wafer-Level Packaging - Instructor: Beth Keser, Intel Corporation 

ROOM: PALM 1

Fan-out wafer level packaging (FO-WLP) technologies have been developed across the industry over the past 15 years and have been in high volume manufacturing for over 10 years. FO-WLP has matured enough that it has come to a crossroads where it has the potential to change the electronic packaging industry by eliminating wirebond and bump interconnections, substrates, leadframes, and the traditional flip chip or wirebond chip attach and underfill assembly technologies across multiple applications. After scale-up and high-volume manufacture of simple single-chip Fan-Out solutions by companies like Qualcomm and Infineon, now many premier semiconductor companies and OEM's have adopted Advanced Fan-Out structures including Apple, MediaTek, HiSilicon, and Xilinx. These companies are leveraging foundry technologies like InFO offered by TSMC as well as OSAT solutions from ASE, Amkor, SPIL, PTI, DECA, and Nepes. This course will cover the advantages of FO-WLP, potential application spaces, advanced package structures available in the industry, technology roadmaps, and benchmarking. The challenges of moving from 300mm FO-WLP to panel will also be discussed.

Course B2: Polymers for Advanced Packages - Instructor: Jeff Gotro, InnoCentrix, LLC 

ROOM: PALM 2

The course will provide an overview of polymers and the important structure-property-process-performance relationships for electronic packaging.  The main learning objectives will be:

1) Understand how polymers are used in electronic packaging; 2) Learn why specific chemistries are used depending on the application, a. Die attach adhesives, b. Underfills (capillary and wafer level), c. Epoxy mold compounds, d. Wafer level packaging, e. High Density Interconnect (HDI) substrates; Participants are invited to bring problems for discussion.

Course B3: Failure Analysis in Semiconductor Package Assembly - Instructor: Tom Dory, Fujifilm Electronic Materials USA 

ROOM: PALM 3

This PDC provides details on current failure analysis methods and reliability testing in package assembly. PDC participants will receive a detailed review of failure analysis methods and reliability testing in assembly. Quickly finding and eliminating package defects and failures due to assembly issues is critical. Package reliability directly affects manufacturing yield, time to market, product performance, customer satisfaction and cost. Many process steps and controls are needed for a high yield and reliable assembly process. A thorough understanding of product and technology reliability principles and mechanisms of failure is essential. Knowledge of defects and failure mechanisms enables a high yielding successful assembly process through material choices, package design, process optimization, and thermo-mechanical considerations. Fault isolation, failure analysis, and materials analysis play a major role in the improvement of yield and reliability. Coordination of engineers from many disciplines is needed in order to achieve high yield and reliability. Each engineer needs to understand the impact of their choices and methods on the final product. This workshop will discuss, using examples, mechanical and thermal failure mechanisms in assembly and detection methods.  
The objective of this workshop is to provide the participants with an overview of the technologies, materials, and processes involved in the latest assembly failure analysis methods.

PDC "Box Lunch" for those taking morning & afternoon classes

ROOM: PALM 4

Course C1: The Evolution of Flip Chip Package Technology - Instructor: Mark Gerber, ASE US, Inc.

ROOM: PALM 1

This PDC course will provide a historical overview and background on the evolution of flip chip packaging as well as short market perspective on this platform. Mobile, Infrastructure, Automotive, High Reliability, Medical and High-Performance Network and Computing all rely on Flip Chip technology to enable their silicon solutions.  Although the use of new technologies such as Fan-Out hold promise for certain applications, flip chip advancements continue to challenge many new technology competitors from a price and reliability perspective and may end up driving hybrid approaches.  Interconnect structure, process flows, materials and package integration process methods for evolving Flip Chip applications will be discussed in detail. Understanding the trade-offs between the different bump structures and package platforms is key in determining the silicon device layout and the type of design rules that can be leveraged for new products. As part of this course, the assembly process details will be discussed and will include Mass Reflow, Thermo-Compression Non-Conductive Paste (TCNCP) bonding and Laser Assisted Bonding. Reliability aspects such as IMC formations and ways to address will also be covered as a key consideration for Interconnect decisions.

Course C2: Chiplet Design and Heterogeneous Integration Packaging - Instructor: John Lau, Unimicron Technology Corp.

ROOM: PALM 2

Chiplet heterogeneous integration (CHI) uses packaging technology to integrate dissimilar chiplets, photonic devices, and/or components (side-by-side and/or stack) with different materials and functions, and from different fabless design houses, foundries, wafer sizes, feature sizes and companies into a system or subsystem. SiP (system-in-package) is very similar to CHI except SiP is simpler, less dense, and larger pitch. For the next few years, we will see more implementations of a higher level of SiP/CHI, whether it is for time-to-market, performance, form factor, power consumption or cost. In this lecture, the introduction, recent advances, and trends in SiP and CHI will be presented. 

CANCELED -- Course C3 (VIRTUAL LIVESTREAM ONLY): Package/Assembly Integrity & Solder Joint Reliability - Instructor: Jennie Hwang, H-Technologies Group

PDC Coffee Break in Foyer

Course D1: Fan-out Wafer/Panel-level Packaging - Instructor: John Lau, Unimicron Technology Corp.

ROOM: PALM 1

Fan-out wafer/panel-level packaging (FOW/PLP) has been getting lots of tractions since TSMC used their integrated fan-out (InFO) to package the application processor chipset for the iPhone 7. In this lecture, the following topics will be presented and discussed. Emphasis is placed on the fundamentals and latest developments of these areas in the past few years. Their future trends will also be explored.  

Course D2 (VIRTUAL LIVESTREAM ONLY): Thermal Management of Electronics - Instructor: Jaime Sanchez, Intel Corporation

ROOM: PALM 2

This course provides the fundamentals of heat transfer applied to the design of thermal systems used to cool electronic components with an emphasis in semiconductor packages. We start with the basic theory of heat transfer and demonstrate simple concepts used today to calculate the cooling requirements for an electronic package and the impact of various parameters on the electronic package. This course covers in-depth heat transfer theory and analysis to give the student a comprehensive understanding of the key modes of heat transfer and their applications. Practical topics such as thermal interface materials, heat sink design and advanced cooling techniques are reviewed.

Course D3: 3D Package Assembly Processes and Technology - Instructor: Tom Dory, Fujifilm Electronic Materials USA

ROOM: PALM 3

This PDC provides details on current and future assembly 3D packaging processes and technologies. The 3D IC and wafer-level packaging area is forecasted to grow to over $2.5 billion by 2016 driven by mobile devices including phone and tablet computers. Advanced packaging requirements require the evolution of back end manufacturing to become more process control driven. The 3D stacked die TSV packaging has advantages, but only in some market segments. In the cell phone market, stacking chips helps to minimize some of the interconnect issues between the logic and the memory chips. Wire bonding remains a key assembly method for 3D memory packages. This workshop will cover 3D and 2.5D (interposer) designs, 3D assembly flow, known good die, KGD, concerns, 3D package testing issues, supply line logistics, thermal management, logic bump out designs, wafer thinning and handling (thermal & laser debonding and residue removal) and interposers with microfluidics cooling built-in. Multichip package options including SiP, SoP and interposer packages will be discussed. The objective of this workshop is to provide the students with an overview of the technologies, materials, and processes involved in the latest 3D and 2.5D assembly processes.

5:30 pm – 7:00 pm

sponsored by

WELCOME RECEPTION

Open to all IMAPS 2021 participants

Flamingo Lawn (Outside - weather permitting)

7:00 pm – 8:00 pm

Sponsored by:

DIVERSITY & INCLUSION TOWNHALL DISCUSSION:
Career Growth During a Global Pandemic

PALM ROOMS 5-6

Moderator/Chair: Erica Folk, Northrop Grumman

Townhall Participants:
Beth Keser, Intel Corp.; Mak Kulkarni, Texas Instruments;
Marqus Patton, SD National Society of Black Engineers; Nicole Wongk, Honeywell

This will be a one-hour townhall – open discussion and panel format. Join us for open and lively conversation around many important topics for all to consider in today‘s challenging pandemic work environment, including:

The importance of diversity within IMAPS
Diversity in Challenges in a virtual workplace
Best practices for diversity and inclusion
How to make an impact in your workplace
And more

8:30 am - 11:30 am

sponsored by

Opening Plenary Session & Keynotes

ROOM: Town & Country A

KEYNOTE 1: 9:00 am - 9:45 am (Virtual Presentation)

Advanced Packaging Architectures: Opportunities and Challenges

Advanced packaging architectures are today widely acknowledged as being increasingly important to drive performance and cost improvements of microelectronics systems.  As a result, several innovative packaging architectures have been announced in recent years.  On-package integration provides a compact, power efficient platform for Heterogeneous Integration of diverse IP that support faster time to market and cost/yield benefits.  In this talk, I will describe current technology envelopes and future scaling directions for representative advanced packaging architectures. Key areas of focus will be (1) interconnect scaling, (2) power efficient high bandwidth signaling including optical interconnects, (3) Hybrid Bonding, (4) test challenges for chiplets/die block assembly, and (5) advanced power delivery technologies.  The talk will conclude with a call for broad collaboration across industry and academia in multiple areas including technology R&D, design, standardization and supply chain development.  

Hamid Azimi, Ph.D., Intel Corporation

Corporate Vice President, Director, Substrate Packaging Technology Development
Dr Azimi leads substrate package technology development organization at Intel and is responsible for developing industry leading substrate package materials, processes, and equipment technologies as well as the associated supply chain capabilities to enable high volume manufacturing for substrates across our 15+ supplier factories. He joined Intel in 1995 and has since served in various leadership roles in Technology Development Organization.  Starting 2010, he led the establishment of Intel‘s first substrate R&D factory in Chandler AZ which became the birthplace of panel level die embedding (EMIB) and the key corner stone for establishing package platforms for Intel data center products. Hamid holds more than a dozen patents and has given numerous talks at international conferences.  He is a board member and the General Chair of International Semiconductor Executive Summit.  In 2014, Hamid received Distinguished Alumni Award from Lehigh University where he completed his PhD in materials Science and engineering.  

9:45 am - 10:15 am

sponsored by

KEYNOTE 2: 10:15 am - 11:00 am

More Moore or More than Moore. An EDA perspective

Over the past 30+ years there’s been a significant shift in the way commercial electronics have been designed.  There are many inflection points that have influenced how consumer electronics and systems products are developed across many vertical markets including transportation, 5G, wireless communications, industrial, medical, and more.  This talk will discuss the impact several drivers including Moore’s Law, as well as advances in the design of semiconductors, systems, and advance packaging.

KT Moore, Cadence Design Systems, Inc.

Vice President
KT Moore joined Cadence in August 2012 and is currently responsible for business development and product marketing for the CPG covering Cadence‘s full suite of custom IC, PCB, and Systems Analysis products. This encompasses several key technology areas including custom IC layout and automation, circuit level simulation, PCB design, and multi-physics analysis and simulation. Prior to joining Cadence, KT spent 12 years with Magma Design Automation. During that time he served 6 years as a Global Account Director, and 6 years as a Vice President of Product Marketing, where he was responsible for business development and marketing for all Magma products. Before joining Magma KT also held various sales positions with EPIC Design Technology and Valid Logic Systems. Prior to his career in EDA, KT spent several years as a logic designer for Texas Instruments. KT received a Bachelor of Science degree in Electrical Engineering and Applied Physics from Case Western Reserve University in Cleveland, OH in 1985.

11:15 am - 1:15 pm

sponsored by

Track 1

Hi-Rel Session 1:
HIGH RELIABILITY PACKAGING, RF, DESIGN

Session Chairs:

Tim LeClair, Cerapax
Ken Kuang, Torrey Hills Tech.

ROOM: TOWN & COUNTRY A

Track 2

Materials Session 1:
NOVEL FABRICATION METHODS

Jeff Gotro, Innocentrix

ROOM: TOWN & COUNTRY B

Advanced Packaging Session 1:
FLIP CHIP

Frank Eberle, Northrop Grumman Corp.

ROOM: TOWN & COUNTRY A

Wafer Level Session 1:
WAFER-LEVEL FAN OUT & ADVANCE RDL

Session Chair:
Irene Popova, Ancosys

ROOM: TOWN & COUNTRY B

7:00 am - 8:00 am

sponsored by

8:00 am - 9:45 am

Day 2 Announcements & Keynotes

ROOM: TOWN & COUNTRY A

KEYNOTE 3: 8:15 am - 9:00 am (Virtual Presentation)

Packaging Technologies for Integrated Photonics

Integrated photonics combine multiple optical and electronic functions onto a single semiconductor chip, shrinking footprint and cost significantly. This enables new applications such as faster and more portable communication devices, quantum computing, smart and minimally invasive surgical devices, personal medical diagnostics, food quality monitoring, autonomous vehicles, space-based systems, the internet-of-things and augmented reality systems. There have been significant developments to realise cost-effective photonic chip fabrication processes, but there now exists a manufacturing bottleneck associated with device packaging which is impeding the growth of these emerging markets. This talk will give an overview of existing photonic and electronic packaging technologies and future challenges. The talk will also present how many of these packaging technologies being brought to commercialisation through a large-scale Pilot Line funded by the European Commission. Called PIXAPP, the Pilot Line provides users with a wide range of advanced photonic and electronic packaging technologies, with the ability to scale manufacturing to medium volumes. PIXAPP is strongly focused on offering standardised packaging technologies, and is working with its global partners to establish a detailed set of packaging design rules and technology roadmap.

Peter O'Brien, Tyndall Institute

Director

Prof. Peter O’Brien is Director of the European Photonics Packaging Pilot Line (www.pixapp.eu), leads the new European Photonics Academy (www.photonhub.eu) and head of the Photonics Packaging & Integration Group at the Tyndall Institute (www.tyndall.ie) at University College Cork in Ireland. His research group develops packaging and device integration solutions for a wide range of photonic-based applications. The PIXAPP Pilot Line, which he coordinates, is currently engaged with over 140 companies from across the world, developing packaging solutions for applications including communications, quantum computing, medical diagnostics and LIDAR. Prof. O’Brien previously founded and was CEO of a start-up company manufacturing speciality photonic systems for bio-imaging applications, which he sold in 2009. Prior to this, he was a post-doctoral scholar at the California Institute of Technology and a research scientist at NASA’s Jet Propulsion Laboratory, where he was involved in the development of submillimetre wave devices for remote sensing applications. He received his degree and PhD in Physics from Trinity College Dublin and University College Cork respectively

KEYNOTE 4: 9:00 am - 9:45 am (Virtual Presentation)

Next Generation Advanced Packaging and Thermo-Mechanical Considerations to Maximize Si Performance

For several decades, microelectronic industries and relevant Academic communities have invested tremendous effort in developing electronics to introduce many breakthroughs and revolutions in packaging technologies and repetitive efforts to address traditional problems. In recent years, slowdown in Moore‘s law scaling and the challenging economics associated with adopting new Silicon nodes has led to an industry emphasis on chiplet-based architectures that require advanced packaging options ranging from MCM to CoWoS® for HPC, Networking, Cloud Services, Emulation and other applications.

Advanced heterogeneous packaging based on 2.5D CoWoS®/3D/Fan-out/Optical or other platforms are required to address various Logic and memory integration.  The inexorable push towards higher performance system in a package solutions coupled with silicon technology scaling and cost challenges is expected to stretch the heterogeneous packaging boundaries much further.   Thermal solution is also becoming an active area of focus as the power levels are expected to push well beyond 500W.

In the presentation we will examine latest Heterogeneous Packaging industry trends with some FPGA examples, challenges and considerations from a product perspective.  Industry roadmap projections do not adequately tackle questions on optimal package configurations that maximize silicon performance while addressing manufacturability, reliability and thermal constraints.  Especially, heterogeneous integration of chiplet or stacked dies in a single package, leads to ever-increasing localization of heat and thermo-mechanical reliability challenges with the package and board integration. This presentation will also touch upon some of trends and challenges in these areas and interplay with the package. 

Suresh Ramalingam, Xilinx

Fellow
Dr. Suresh Ramalingam graduated in 1994 with a Ph.D. in Chemical Engineering from Massachusetts Institute of Technology, Cambridge. He holds 40 US Patents, 30+ publications, 2013 SEMI Award, Ross Freeman Award for Technical Innovation, ECTC 2011 Conference Best Paper Award, IMAPS 2013 and 2014 Conference Best Paper Awards for 2.5D/3D and contributed a book chapter on 3D Integration in VLSI Circuits.  He started his career at Intel developing Organic Flip Chip Technology for Micro-processors which was implemented on Pentium II (Intel’s first flip chip product) in 1997. The effort received personal recognition from then CEO Craig Barrett.  As one of the co-founders and Director of Packaging Materials at Scion Photonics started in 2000, he helped develop DWDM modules used by major communication companies. JDS Uniphase acquired Scion Photonics in 2002.  After joining Xilinx in 2004, he has experienced various roles from Substrate Technology & Sourcing, Design Management to Packaging Technology Development.  As a Xilinx Fellow, he currently manages Advanced Packaging Interconnect Technology Development including TSV/3D/Optical for Xilinx FPGA products.   Thermal and Mechanical Enablement at Board/System Level is a key focus area to push the power/performance envelope and this is an area he currently manages for Xilinx Alveo and SOM products.

9:45 am - 10:15 am

sponsored by

New Content

TRACK 1

Wafer Level Session 2:
WAFER / HYBRID BONDING

TRACK 2

Wafer Level Session 3:
WLCSP (FAN IN AND ADVANCE MATERIAL)

10:15 am - 10:40 am

11:45 am - 1:30 pm

sponsored by

TRACK 1

Advanced Packaging Session 2:
INVITED SESSION: OPTICAL CO-PACKAGING
** Hybrid Session **

TRACK 2

Materials Session 2:
ADVANCED INTERCONNECTS / WIRE BOND

Mark Wade, Ayar Labs

** Virtual Presentation **

Katarzyna awniczuk, Bright Photonics B.V.

** Virtual Presentation **

3:25 pm - 4:15 pm

sponsored by

INVITED SESSION: OPTICAL CO-PACKAGING
** Hybrid Session **

Wafer Level Session 4:
PANEL-LEVEL FAN OUT

Marika Immonen, TTM Technologies Inc.

** Virtual Presentation **

ROOM: TOWN & COUNTRY A

Lithography Solutions for Submicron Panel-Level Packaging
Doug Shelton, Canon USA

ROOM: TOWN & COUNTRY B

Bardia Pezeshki, AvicenaTech

** Virtual Presentation **

5:45 pm - 6:45 pm

sponsored by

6:45 pm - 8:30 pm

ROOM: TOWN & COUNTRY A

sponsored by

EVENING KEYNOTE & PANEL SESSION

KEYNOTE: Challenges and Opportunities of Packaging Fab Near the End of Moore's Era (VIRTUAL PRESENTATION)

While the semiconductor industry has relied on CMOS scaling for decades, heterogeneous integration of a diverse set of technologies is now an important way to drive optimum power-performance-area-cost (PPAC) and turn-around-time (TAT) beyond what was possible with monolithic integration only. Various chiplet packaging solutions, such as 2D, 2.5D, 3D and 3.5D are necessary to develop fine pitch interconnection evolutions with the Cu hybrid bonding or fine pitch microbump inteconnection.

In this presentation, package FAB solutions are to be introduced and discussed in terms of challenges and opportunities for emerging high-end computing and mobile processor platforms. In addition, Fanout WLP, RDL interposer, high-performance 3D SIP and Integrated Stacked Capacitor (ISC) are introduced.

Corporate VP/Package Technology Planning, Test & System Package
Dr. YOON is currently working as Corporate VP/Head of Team of Package Technology Planning, Test & System Package, Samsung Electronics. Prior to joining Samsung, He was director of group technology strategy, STATS ChipPAC. He also worked deputy lab director of MMC (Microsystem, Module and Components) lab, IME (Institute of Microelectronics), A*STAR, Singapore. YOON received Ph.D degree in Materials Science and Engineering from KAIST, Korea. He also holds MBA degree from Nanyang Business School, Singapore. He has over 300 journal papers, conference papers and trade journal papers, and over 20 US patents on microelectronic materials and electronic packaging. Served as technical committee member of various international packaging technology conferences, EPTC, ESTC, IMAPS, IWLPC and SEMI.

PANEL: NEXT GENERATION PACKAGES: ARE WE READY?

Moderator: Jan Vardaman, President and Founder of TechSearch International, Inc.

New package options are required to meet the needs of advanced silicon nodes and cost reduction.  Adoption of Co-packaged optics is anticipated.  The industry requires a health infrastructure to meet future packaging needs including heterogeneous integration and chiplets.  Are we ready?  What infrastructure issues need to be addressed?  This panel discusses challenges in meeting the needs of next generation packaging and provides insight into potential solutions.

Tom DeBonis, Intel – Engineering TD Manager, Assembly/Test Technology Development
Ravi Agarwal, Facebook - Technical Sourcing Manager (VIRTUAL)
Suresh Ramalingam, Xilinx - Fellow (VIRTUAL)
Ashkan Seyedi, Nvidia – Silicon Photonics Product Architect (VIRTUAL)
Seungwook Stewart Yoon, Samsung Electronics - R&D Strategy, Corporate VP/Head of Team (VIRTUAL)

Includes Beer, Wine and Appetizers - for those attending in San Diego!

Jean-Christophe Eloy, Yole Développement
President and CEO
Jean-Christophe Eloy is President and CEO of the Yole Développement company. Created in 1998, the market research & strategy consulting company has grown to become a group of companies providing marketing, technology and strategy consulting, media in addition to corporate finance services. His mission is to oversee the strategic direction of Yole Group of Companies.

With System Plus Consulting, Blumorpho, PISEO and Yole Développement, Yole Group of Companies has developed a unique understanding of technologies to accurately evaluate markets, applications, solutions and strategies.

With more than 70 analysts, including PhD and MBA qualified industry veterans, the group collects information, identifies trends, challenges, emerging markets, and competitive environments and then turns that information into results to give a complete picture of the industry’s landscape.

All year long, Jean-Christophe builds deep relationships with leading semiconductor companies, discussing and sharing information across his global network. His aim is to get a comprehensive understanding of their strengths and guide their success.

KEYNOTE 6: 9:00 am - 9:45 am (Virtual Presentation)
A NEW ERA FOR GLASS IN MICROELECTRONICS PACKAGING

For glass, it would be inappropriate to speak of a new material in microelectronics. It is considered one of the oldest man-made materials and is also regularly used in electronic packaging already. However, if we look at the fundamental material properties of glass, the only question that really arises is: why isn't it used in a greater number of applications? The answer to the question lies in the widespread believe that glass is difficult or uneconomical to process on a microscale.

This presentation will describe how recent developments in the field of laser-induced deep etching are helping to enable novelle packages and bring glass to a new era in micro-electronics.

12:15 pm - 3:00 pm

ROOM: TOWN & COUNTRY A

(PIZZA Lunch for those in room)

Special Invited Session: Heterogenous Integration Roadmap           
Session Chair: Bill Chen, ASE
Overview                                        Bill Bottoms / Bill Chen
Medical Health & Wearable          Mark Poliks
MEMS & Sensor Integration          Shafi Saiyid & MaryAnn Maher
Supply Chain                                  Tom Salmon
Security                                           Sohrab Attabjahani
Round Table Discussion + Q&A from Chat