Symposium Program

PROGRAM AT A GLANCE

       Conference      
October 3 - 6, 2022

            Exhibition         
October 4 - 5, 2022

 Professional Development Courses 
October 3, 2022

IMAPS is pleased to announce the technical program for IMAPS 2022. The program includes keynote presentations, Professional Development Courses, technical presentations and Posters. Learn more below!

MONDAY, October 3 - Professional Development Courses (PDCs)

All times listed as Eastern Time

All PDCs held Monday, October 3, 2022 Eastern Time and are an additional fee
8:00 am – 10:00 am

Course A1: Polymers for Wafer Level Packaging - Instructor: Jeff Gotro, InnoCentrix, LLC

Course A2: Modern Wire Bonding in Package Assembly - Instructor: Tom Dory, Fujifilm Electronic Materials USA  

Course A3: Flip Chip Tech - Instructor: Mark Gerber, ASE US, Inc.

10:00 am – 10:30 am

PDC Coffee Break in Foyer

10:30 am -12:30 pm

Course B1: Chiplet Design and Heterogeneous Integration Packaging - Instructor: John Lau, Unimicron Technology Corp. 

Course B2: Wire Bond Process Development and Optimization - Instructor: Henri 

Course B3: Chip Packaging Processes and Materials - Instructor: Syed 

12:30 pm – 1:00 pm

PDC "Box Lunch" for those taking morning & afternoon classes

1:00 pm -3:00 pm

Course C1: Fan Out for Advanced Packaging Applications - Instructor: John Hunt

Course C2: System-in-Package (SiP) - System Solutions Through Miniaturization - Instructor: Mark Gerber, ASE US, Inc.

Course C3: Fundamentals of Thermal Management - Instructor: Rita

3:00 pm – 3:30 pm

PDC Coffee Break in Foyer

3:30 pm -5:30 pm

Course D1: Advances in Fan-Out Wafer Level Packaging - Instructor: Beth Keser, Intel Corporation

Course D2: 3D Flip Chip Package Technology and Assembly Processes - Instructor: Tom Dory, Fujifilm Electronic Materials USA  

Course D3: Qualification Formalism for Markets Demanding High Quality & Reliability Standards - Instructor: Shubhada

5:30 pm – 7:00 pm


WELCOME RECEPTION

Open to all IMAPS 2022 participants

7:00 pm – 8:00 pm


IMAPS DEI TOWNHALL DISCUSSION and RECEPTION:

Equity vs. Equality in the Workplace

Chair:

Chair: Robin Davis, Deca Technologies
Committee: Erica Folk, Northrop Grumman; Beth Keser, Intel; Dan Krueger, Honeywell; Urmi Ray, iNEMI; Nicole Wongk, Honeywell

This will be a one-hour townhall – open discussion and panel format. Join us for open and lively conversation around many important topics for all to consider in today‘s challenging work environment, including the important differences between equity and equality in the workplace.

PANELISTS:

Rebeca Jimenez, Amkor Technology

Additional Panelists Announced Soon

Food & Drink Provided

TUESDAY, OCTOBER 4

7:00 am - 5:30 pm
Registration Open
7:30 am - 8:30 am

BREAKFAST & COFFEE IN FOYER

8:30 am - 11:30 am


Opening Plenary Session & Keynotes


KEYNOTE 1: 9:00 am - 9:45 am

TITLE

Speaker

9:45 am - 10:15 am


COFFEE BREAK IN FOYER

KEYNOTE 2: 10:15 am - 11:00 am

TITLE

Speaker

11:00 am - 4:30 pm

Exhibit Hall Open

11:15 am - 1:15 pm

NETWORKING AND LUNCH IN EXHIBIT HALL

1:15 pm - 4:30 pm

Afternoon Technical Sessions

A – SiP / Design / Manufacturing Optimization

Track Chairs:
Dongshun Bai, Brewer Science;
Bora Baloglu, Amkor Technology;
Fang Luo, Stony Brook University

B - Wafer Level/Panel Level (Advanced RDL)

Track Chairs:
Tarak Railkar, Qorvo;

Rey Alvarado, Qualcomm;
Mohan Kathaperumal, Georgia Tech.

C -High Performance-High Reliability

Track Chairs:
Erica Folk, Northrop Grumman;

Rajiv Iyer, Medtronic;
Ivan Ndip, Fraunhofer IZM

D -  Advanced Packaging (Flip Chip/2.5D/3D/Optical)

Track Chairs:
Frank Eberle, Northrop Grumman;

Jaimal Williamson, Texas Instruments;
Rahul Panat, Carnegie Mellon University

E - Advanced Process  & Materials (Enabling Technologies)

Track Chairs:
Mark Hoffmeyer, IBM;
Habib Hichri, Ajinomoto;
Benson Chan, Binghamton University

TPM1 - DESIGN, MODELING & SYSTEMS SIMULATION
Session Chairs:
Karthik Dhandapani, Qualcomm;
Lei Fu, AMD
TPM2 - WAFER-LEVEL-FAN-OUT AND ADVANCED RDL
Session Chairs:
Frank Wei, Disco;
Ram Trichur, Henkel;
Ravi Agarwal, Meta
TPM3 – EXTREME ENVIRONMENT
Session Chairs:
Zhenzhen Shen (Jenny), Reality Labs (Meta Platforms, Inc.);
Otto Fanini, Halliburton Energy Services; Nakul Kothari, SkyWorks Solutions
TPM4 – INVITED SESSION: OPTICAL CO-PACKAGING
Session Chairs:
Tolga Tekin, Fraunhofer IZM;
Vivek Raghunathan, Xscape Photonics
TPM5 – ADVANCE PROCESSES AND MATERIALS
Session Chairs:
Aric Shorey, Menlo Microsystems;
Sylvain Pharand, IBM;
Varun Soman, Binghamton University
Simple Solution to Estimating and Predicting Transient Current in Small Signal AC Circuits
Virgil Ganescu, York College of PA
Inspection Solution for 2um RDL from Wafer-Level to Panel-Level Fan-out Process
Leon Lin, Onto Innovation (Anderson Liu; Jay Chen; Maruko Wu; Cheolkyu Kim; Zhuan Liu)
Towards Ultra-High Stability: MEMS Inertial Sensors
Amrit Abrol, Analog Devices
Electro-Optical Co-design for Future Electronic & Photonic System of Chips Architectures               
Twan Korthorst, Synopsys
Novel Electroformed Ni-Au alloy for High Temperature Semiconductor Test Structures
Robert Hilty, Xtalic Corporation (Jane Freydina)
An Organic Package Designer's Guide to Transitioning to FOWLP and 2.5D Design
Bill Acito, Siemens EDA
Carrier technology solution for fan-out wafer level & panel level package
Yoshinori Matsuura, Mitsui Mining & Smelting Co.,LTD., (Joji Fujii)
Electrically Insulative Film Adhesive with Enhanced Thermal Performance to Assemble High Power Density Electronic Device
Yuan Zhao, Henkel Corporation
Electronic and Photonic Heterogeneous Integration and Fiber-Interconnection using Self-Aligning Stitch-Chip Technology 
Muhannad Bakir, Georgia Tech University
Optimization of Additively Manufactured Interposers for DC and RF Applications in Printed Circuit Boards
Emily Lamport, University of Massachusetts Lowell (Andrew Luce; Yuri Piro; Susan Trulli; Alkim Akyurtlu)
A Comprehensive Evaluation of Al Heavy Wire Bonding and Ribbon Bonding Application in high power WBG Power Modules
Yang LI, Stony Brook University (Fang Luo; Michael McKeown)
Identification of copper RDL reliability concerns related to PBO quality
Terence Collier, CVInc
A Lead-Free Lower-Temperature Solder Paste for Wafer-Level Package Application
Hongwen Zhang, Indium Corporation (Tyler Richmond)
Solder-Assisted Self-Alignment and Precision Thermode Bonding for Passive Optical Co-Packaging
Hermann Oppermann, Fraunhofer IZM
Analysis of Surface Roughness Issues in Printed RF Devices
Yibo Li, University of Massachusetts Lowell (Yuri Piro; Susan Trulli; Steven Lardizabal; Alkim Akyurtlu)
Assembly Solutions for Cost-Effective Heterogeneous Integration with Disparate Die Types
Glenn Farris, Universal Instruments Corp.
Warpage and Stress Behaviors of Multiple Large Chips during Fan Out Package Process Based on Finite Element Analysis
Hu Zhen, leslie.hu (Chen Haijie; Geng Fei; Xu Hong; Guo Liang; Wang Hong; Liu Haoyu)
Advancing Reliable High-Temperature Electronics through Compatible Material Interfaces
Jacob Kupernik, Ozark Integrated Circuits, Inc. (Matt Bakowski; Nick Chiolino; Matt Barlow; A.M. Francis)
Optical, Photonic and Quantum Integration in Hyperscale Data Centres of the Future
Richard Pitwon, Resolute Photonics
Substrate Surface Chemistry ? Insights To Understanding Adhesive Performance
Doug Katze, Henkel Corporation
Predictive Modeling of Burn-in-Testing (BIT): to BIT or not to BIT?
Ephraim Suhir, Portland State University
A novel hybrid method to integrate delicate MEMS components into a FOWLP
Marc Dreissigacker, TU Berlin Microperipheric Center
Silicone Migration Risks and Mitigation in Thermal Materials
Sanjay Misra, Henkel Corporation
Programmable Photonics: Enabling the Smart Operation of Optical Chips
José Capmany, iPronics, Programmable Photonics  
An Evaluation of Bath Life Effects on Photoresist Removal for Wafer Level Packaging
Joel Bahena, Veeco Instruments - Precision Surface Processing (Phillip Tyler; John Taddei; Muthumanickam Sankarapandian; Jamie Prudhomme; Karthikeyan Pillai; Abdullahi Said; Christopher Carr;
Dario Goldfarb; Chris Waskiewicz; Qianwen Chen)
FEA Assisted Optimization of Bump Shear Test Method for Assessment of BEOL Mechanical Integrity and White Bump Risk
Moon Soo Lee, Samsung Foundry (Min Kim; Wungwon Jung; A-Ram Kang; Myeong-soo Yeo; Shinyoung Chung; Eun-cheol Lee) 
Commercialization of Micro-Transfer Printing for III-V Heterogeneous Integration
David Gomez, X-Celeprint (Tanya Moore; James Thostenson; Kevin Oswalt; Ron Cok; Tanya Moore; James Thostenson)
Optimization of reflow profiles and warpages for extreme extension of mass reflow
JIWON SHIN, Samsung Electronics (Dong-uk Kwon)
TBD
Elad Mentovich, nVidia
Wide process latitude, Pb-free low temperature co-fire ceramic (LTCC)
Brian Laughlin, DuPont Microcircuit and Component Materials (Ahmed Salah; Russell Anderson; Young Yoon; Brad Schickling)        

3:40 pm -
4:30 pm

BREAK IN EXHIBIT HALL

5:30 pm -
7:00 pm

POSTERS HAPPY HOUR

FCCSP Warpage Scope Evaluation for  5G Product with Advanced Wafer Node
Tzu-Chi Zeng, Siliconware Precision Industries Co., Ltd


Open-Cavity Plastic Packages: A Robust Solution for High-Reliability Applications
Sam Sadri, QP Technologies (Tom Tammen)


New Packaging Technology for 2-dimensional VCSEL Arrays and Their Electro-Optical Performance and Applications
Rainer Dohle, Dr. Rainer Dohle (Maximilian Wallrodt; Gerold Henning; Cristoph Greus; Christian Neumeyr; Juergen Rosskopf; Robert Hohenleitner)


Heterogeneous Integration of III-V Lasers in a 300mm CMOS Manufacturing Line
Sarah Baranowski, The Research Foundation for State University of New York (Anh Nguyen; Seth Kruger; Lewis G Carpenter; Amit Dikshit; Colin McDonough; David L Harame)


Development of high throughput solderable surface mount free space optical interconnect module for co-packaged processor
Venkata Ramana Pamidighantam, LightSpeed Photonics (Rohin Kumar Yeluripati)


Development of robust sensor packages for autonomous underwater vehicles
Karl-Friedrich Becker, Fraunhofer IZM (Marcus Voitel; David Schütze; Thanh Duy; Malte Spanier; Ole Hoelck; Martin Schneider-Ramelow)

Polymer waveguide for co-packaged optics in data centers
Yi Shen, DuPont Electronics and Industrial (Michael Gallagher; Shourya Jain; Kondoh Masaki; James Ryley; Fazel Zare Bidoky; Zhebin Zhang)

Assembly Solutions for Cost-Effective Heterogeneous Integration with Disparate Die Types
Glenn Farris, Universal Instruments Corporation


3D Silicon Interposer for Terabit/s Transcievers based on high-speed TSVs
Bogdan Sirbu, Fraunhofer IZM (Kai Zoschke; Stéphane Bernabé; Quentin Wilmart; Tolga Tekin)

Current Trends and Challenges in Vertical Optical Interconnects
Drew Weninger, Massachusetts Institute of Technology (Samuel Serna Otalvaro; Lionel Kimerling; Anuradha Agarwal)


Novel Micro-Textured Film Offers Promise in Universal Handling of 3D Devices
Raj Varma, Delphon

Identify the risks with REACH SVHC in IC package
Renata Hsiao, Siliconware Precision Industries Co., Ltd. (Fenny Liu; Hangung Chen; Liang-Yih Hung; Yu Po Wang)

Paving the Way for HDBU to Rule the Day
Samuel Massa, Northrop Grumman

Mixed reaction gold as versatile plating solution for ENIG, ENEPIG and EPAG plating
Britta Schafsteller, Britta Schafsteller (Mario Rosin; Timo Schlosser; Gustavo Ramos)

WEDNESDAY, OCTOBER 5

7:00 am - 6:30 pm

Registration Open

7:00 am - 8:00 am

BREAKFAST & COFFEE IN FOYER

8:00 am - 9:45 am

Day 2 Announcements & Keynotes

KEYNOTE 3: 8:15 am - 9:00 am

TITLE

Speaker

KEYNOTE 4: 9:00 am - 9:45 am

TITLE

Speaker

9:45 am - 10:15 am

COFFEE BREAK IN FOYER

10:15 am - 11:40 am

Morning Technical Sessions

WAM1 - ADVANCED MATERIALS
Session Chairs:
Luke Prenger, Brewer Science;
Jay Zhang, Corning
WAM2 - FAN-OUT RDL AND ASSEMBLY PROCESSES
Session Chairs:
Li-san Chan, Heraeus;
Padam Jain, Google
WAM3 – HIGH RELIABILITY
Session Chairs:
Ken Kuang, Torrey Hills Tech.;
Vikram Venkatdri, Analog Devices;
Irene Popova, Ancosys
WAM4 - INTERCONNECTS
Session Chairs:
Lyndon Larson, DuPont Electronics
Shubhada Sahasrabudhe, Intel
WAM5 – POWER SUBSTRATE TECHNOLOGY
Session Chairs:
Doug Hopkins, North Carolina State University; Doug Shelton, Canon USA
A Drop-in High-Temperature Lead-Free Solder Paste that Outperforms High-Pb Pastes in Power Discrete Applications
Hongwen Zhang, Indium Corporation (Tyler Richmond)
Assembly Technology for FO-MCM with HBM in HPC Application
Shuai-Lin (Bradley) Liu, SPIL (Nicholas Kao; George Pan; David Lai; Yu-Po Wang)
Electromigration Risk Assessment and Circuit Optimization using Innovative Multiphysics Modeling
Chongyang Cai, Google (zhi yang; Yuan Li; Padam Jain; Terry Kang)
Investigation of electroless copper plating with high plating coverage in small BVH for next generation fine pattern SAP
Shinichiro Yoshida, C. Uyemura & Co., Ltd. (Tomoharu Nakayama; Hisamitsu Yamamoto)

Solid-State Power Baseplates
Jim Fraivillig, Fraivillig Technologies

Development of a Photopolymer-Based Dielectric Nanocomposite for High Resolution Direct-Write Processes
Yuri Piro, University of Massachusetts (Christopher Aerias; Andrew Luce; Emily Lamport; Yibo Li; Susan Trulli; Alkim Akyurtlu)
Maskless direct write lithography for 3D wafer-level-system-integration
Frank Windrich, Fraunhofer IZM-ASSID (Achim Jehle; Sven Preuss)
On Excess CO2 within a Hermetically Sealed 14-Pin Butterfly Package: Solubility of CO2 within Fluorocarbon Liquids
Mark De Luna, Northrop Grumman (Todd Uramoto)
Microstructural Characterization of Sn57Bi1Ag Solder Alloy Joints
Sarangapani Murali, HERAEUS MATERIALS SINGAPORE PTE LTD (Evonne Lim Yee Weon; Miew Wan Lo; Abito Bayaras Danila; Yee Ting Lo; Loke Chee Keong; Kang SS Sungsig)

A New Look for SiC!
Frank Muscolino, Advanced Assembly Technology

Advancements, Versatility, and Flexibility of Dual-Layer Material System for Advanced Packaging Applications
Luke Prenger, Brewer Science, Inc. (Andy Jones; Dongshun Bai; Matt Koch)
Printing of Micro and Nanoscale Heterogenous Integrated and Advanced Electronics Packaging
Ahmed Busnaina, Nano OPS, Inc.
A Physics-of-Failure Investigation into Flip Chip Reliability Based on Lead Free Solder Fatigue Modeling
Sean Brinlee, CAES
A high-uniformity, high-purity copper pillar ECP process with limited acid concentration
Pingping Ye, MacdermidAlpha (Adam Letize; Jianwen Han; Stephan Braye; Ashley Kuppersmith; Kyle Whitten; Thomas Richardson; Elie Najjar)

Understanding Criticality of Thermal Performance in Thermal Interface Material Applications
Rita Mohanty, Henkel Corporation (John Prindl)

TAT PCB for High Frequency Electronics
Colin Daly, Corning (Geriant Owen; Timothy Orsley)
Development of all new structure of Dicing Die Attach Film (DDAF)  for  Stealth Dicing and Cool Expansion processes
Wataru Iwaya, LINTEC OF AMERICA, INC. (Yosuke Sato; Misaki Sakamoto; Masanori Yamagishi; Naoya Saiki)
Simulation and Experimental Study on Edge Bonding Shape for BGA Packages with High Reliability
Yasuhiko Kato, Showa Denko (Hiroyuki Hamagami; Tomoaki Shibata; Kohei Seki; Ryota Sato)
Dielectric Property Effect with Dielectric Constant for Millimeter Wave Antenna Design
Chih Yuan Shih, Teny (Chia Chu Lai; Yu-Po Wang)
Interfacial Diffusion Mechanism between ALD Al2O3 passivation/Cu in Direct Bonded Copper Substrate for Power Electronics
Kirak Son, Electronics and Telecommunications Research Institute (Aesun Oh; Hyun-Cheol Bae)

11:45 am - 1:30 pm

NETWORKING & LUNCH IN EXHIBIT HALL

1:30 pm - 5:45 pm

Afternoon Technical Sessions

WPM1 - ADVANCED PACKAGING & RELIABILITY
Session Chairs:
Sunny Agarwal, ITW EAE;
Varughese Mathew, NXP Semiconductors
WPM2 – WAFER LEVEL CHIP SCALE PACKAGING AND ADVANCED MATERIALS
Session Chairs:
SooSan Park, JCET;
Linda Bal, TechSearch International
WPM3 – INVITED SESSION: HETEROGENEOUS INTEGRATION ROADMAP
Session Chairs:
Bill Chen, ASE Group;
Benson Chan, Binghamton University
WPM4 – FLIP CHIP
Session Chairs:
Karl Freidrich Becker, Fraunhofer IZM
Jim Will, SkyWater Technology
WPM5 – WIRE BONDING
Session Chairs:
Martin Schneider-Ramelow, Fraunhofer IZM; Mike McKeown, Hesse Mechatronics
Board Level Reliability of Flipchip Package
Nishant Lakhera, NXP Semiconductors (Andrew Mawer; Mollie Benson)
Novel Temporary Bonding Film Adapted to Xenon Flash Lamp De-bonding System for FOWLP Application
Hiroaki Matsubara, Matsubara-san (Tomoaki Shibata; Yuta Akasu; Shogo Sobue; Ayaka Kuroda; Saeko Ogawa)
Intro to heterogeneous Integration Roadmap
Bill Chen    Tim Lee
Pre-applied underfill Technique for Fine-pitch Cu Pillar 3D Die Stacking to Enable 2.5/3D Advanced Packaging
Nicholas Lay, Northrop Grumman Corp (Kaysar Rahim; Melissa Holliday; Nicholas Dinapoli)
High Robustness of Coated-Ag Wire Bonding
Sarangapani Murali, Heraeus Materials Singapore Pte Ltd (Evonne Lim Yee Weon; Dhayalan Mariayppan; Miew Wan Lo; Joanne Chong Mei Hoe; Senthilkumar Balasubramanian; Kang SS Sungsig)
Investigation of CuAl IMCs Corrosion in Chloride Environment and its Prevention Strategy
John Alptekin, University of North Texas (Eswar Gopalakrishnan; Dinesh Kumar Kumaravel; Kevin Antony; Oliver Chyan; Varughese Mathew)
Protected Wafer Level Chip Scale Packaging (P-WLCSP)
Douglas Hackler, American Semiconductor, Inc. (Ed Prack; Randall Parker)
Aerospace and Defense                
Bill Bass      Tim Lee
Mass Reflow Solution for CTE mismatch related defects for flip chip substrate processing
Thomas Tong, BTU International INC (Richard Malen)
Insulated, Passivated & Adhesively-Promoted Bond Wire Using All-in-One Al2O3 Coating
Soojae Park, Samsung Electronics Company
A CLOSED FORM METHOD TO ESTIMATE NUMBER OF FATIGUE CYCLES AND IDENTIFY HIGH RISK LEAD-FREE SAC SOLDER JOINTS
Tuan Nguyen, Raytheon Technologies
Reconfigurable NEMS based Advance packaging for Anti Reverse engineering and counterfeiting
Aslam A. Khan, Aslam (Keon Sahebkar; Ryan F Need; Mark Tehranipoor; Navid Asadizanjani)
Reliability
Abhijit Dasgupta
Optimization of the Microstructure for Copper-to-Copper Direct Bonding by Electrodeposition Processes
Ralf Schmidt, Atotech Deutschland GmbH
Digital Twins and Smart Manufacturing for Wire Bonding
Basil Milton, Kulicke & Soffa Industries, Inc. (Ray Cathcart; Odal Kwon; Pavel Shusharin; Ivy Qin)
Die-embedded packaging using Corning multi-layered glass
Choon-Kon
Hyung-Soo (Alex) Kim
NOW: Moon, Corning Technology Center Korea (Yu Xiao; Jong-Min Yook; Hyun-Je Chang; Hyung-Soo Moon)
Prevention of Cu electrolytic migration defects on RDL by a Cu-selective passivation to enhance reliability
Ashish Shivaji Salunke, University of North Texas (Kaushik Akula; Subiksha Jayakumar; Shaurya Kumar; John Alptekin; Oliver Chyan; Ninad Shahane)
MEMS       
Shafi Saiyed, Mary Ann Maher
Impact of FCBGA substrate stack-up on BLR performance
Jaimal Williamson, Texas Instruments (Yutaka Suzuki; Ron Eller)
Metal Oxide Removal Using Atmospheric Pressure Plasma Technology For Electronic Applications
Daphne Pappas, Plasmatreat USA (Andrew Sy; Ryan Robinson; Richard Burke)
Glass Substrate for Co-Packaged Optics
Lars Brusberg, Corning Research & Development Corporation (Ekin Kocabas; Jason Grenier; Lucas Yeary)
New Photo-Definable Polyimide with High Aspect Ratio Pattern Capability
Masao Tomikawa, Toray Industries (Keigo Kato; Yoshiko Tatsuta; Kazuyuki Matsumura; Akira Shimada)
Co-Design
Jose E.Schutt-Aine       Chris Bailey
Experiment-Simulation Correlation of a Flip Chip Package With Non-Uniform Power Distribution
Eric Ouyang, JCET Global (WEIKUN-JIMMY He; andras vass-varnai)
Atomic Mechanism for Ultrasonic Wire Bonding
Henri Seppanen, Kulicke & Soffa Industries (Milad Khajehvand; Panthea Sepehrband; Peter Klaerner)
Development of high performance flip chip ball grid array (FCBGA) packages for automotive application processors
Gaurav Sharma, NXP Semiconductors
Glass in wafer- and panel- level packaging: On the route towards industrialization.
M. Letz, Schott AG (Tobias Gotschke; Bernd Hoppe; Fabian Wagner; Ulrich Peuchert; David Vanderpool)
Automotive
Vikas Gupta
Electroplated Aluminum Pillars for Ultrasonic Flip Chip Bonding
Silvia Braun, Fraunhofer ENAS (Imants Cirulis; Jan Erik Liedtke; Karla Hiller; Maik Wiemer; Harald Kuhn) 
Algorithm for Ultrasonic Wire Bond Outlier Classification
Pedro Villa, Kulicke&Soffa (Henri Seppaenen)

3:25 pm - 4:15 pm

BREAK IN EXHIBIT HALL

5:45 pm - 6:45 pm

HAPPY HOUR IN EXHIBIT HALL

  

THURSDAY, OCTOBER 6

  

7:00 am - 8:00 am

BREAKFAST & COFFEE IN FOYER

8:00 am - 9:45 am

Announcements & Keynotes

KEYNOTE 5: 8:15 am - 9:00 am


TITLE


Speaker

KEYNOTE 6: 9:00 am - 9:45 am

TITLE   

Speaker

9:45 am - 10:15 am


COFFEE BREAK IN FOYER

10:15 am - 11:40 am

Morning Technical Sessions

THAM1 - MANUFACTURING / PROCESS OPTIMIZATION
Session Chairs:
Santosh Kudtarkar, Analog Devices;
Amol Deshpande, Wolfspeed
THAM2 - MANUFACTURING CONSIDERATIONS
Session Chairs:
Vivek Dutta, Mitsui Mining & Smelting Co. Ltd.; Gengxin Zhang, Qualcomm
THAM3 – HIGH POWER
Session Chairs:
Konstantin Yamnitskiy, Medtronic;
Tim LeClair, Cerapax
THAM4 – HETEROGENEOUS INTEGRATION
Session Chairs:
Arsalan Alam, UCLA CHIPS / AMD
Manish Dubey, AMD
THAM5 - INTERCONNECT
Session Chairs:
Jeff Gotro, Innocentrix;
Kevin Demartini, DuPont
Additive Manufacturing in High-frequency Electronics Packaging
Christopher Areias, University of Massachusetts Lowell (Emily Lamport; Yuri Piro; Alkim Akyurtlu)
Design of Wafer Level Solder Seals - A Surface Energy Perspective
Thomas F. Marinis, Charles Stark Draper Laboratory (Joseph W. Soucy)
Analysis and Validation of GaN-FET Output Capacitance Related Switching Losses in an Extreme Temperature Buck Converter
Martijn S Duraij, Techincal University of Denmark (Gabriel Zsurzsan; Arnold Knott)
Using ADKs to enable early-stage chiplet-to-chiplet  interface compliance
John Park, Cadence Design Systems, Inc. (Ken Willis)
A Hybrid Pressure-less Silver Sintering Technology for High-power Density Electronics
Yuan Zhao, Henkel Corporation (Bruno Tolla; Douglas Katze)
Investigating Optimal Process Parameters for Ultra-Fine Solder Paste Printing in SiP Assembly
Evan Griffith, Indium Corporation (Casey Rowland; David Sbiroli; Jonas Sjoberg)
Fabrication of Panel-Level Glass Substrates with Complete Design Freedom using LIDE
Rafael Santos, LPKF Laser & Electronics (Nils Anspach; Norbert Ambrosius; Stephan Schmidt; Roman Ostholt)
Double Sided Integrated GaN Power Module with Double Pulse Test (DPT) Verification
Sourish S Sinha, North Carolina State University (Tzu-Hsuan Cheng; Douglas C Hopkins)
Status and Outlooks of 2.3D IC Integration
John Lau, Unimicron
Study for Bonding Technology by Electroplated Nano porous Cu Structure
Daiki Furuyama, Mitsubishi Materials corporation (Takuma Nakagawa; Junta Inoue; Koji Tatsumi; Sho Nakagawa; Takuma Katase)
Direct-Write Printed Wearable Metasurfaces
Adria Kajenski, University of Massachusetts Lowell (Shahriar Khushrushahi; Guinevere Strack; Alkim Akyurtlu)
A novel analytical method of Thallium determination in gold electrodeposition
Jingjing Wang, ECI Technology (Patrick Saitta; Eugene Shalyt)
Design to cost Ag free silicon nitride AMB substrate for automotive power module applications
Habib Mustain, Heraeus Electronics (André Schwöbel; Benjamin Fabian; Daniel Schnee; Anton Miric)
Power Envelope Analysis for the Thermal Optimization of a Chiplet Module
Eric Ouyang, JCET Group (Xiao Gu; Yonghyuk Jeong; Michael Liu)
Failure Analysis of of SnBi based Solder Joints during Current Stressing: Changes in Electrical Resistance and Microstru
Eric Cotts, SUNY Binghamton (Faramarz Hadian; Javier Flores; Sitaram Panta)
Bridging the Interconnect Gap for High Performance Computing using an M-Series Embedded Cache Interposer
Benedict San Jose, Deca Technologies, Inc (Robin Davis; Tim Olson)
Study on CPI behaviors of X Dimension Fan-Out Integration (XDFOI) packages
Chen Haijie, JCET (Hu Zheng; Wang Chen; Pan Hao; Xu Li; He Ming; Xie Jielei)
Smaller than MLCC: CCW (Ceramic Capacitor Wire)
Soojae Park, Samsung Electronics Company
Heterogeneous Integration Hybrid Substrate with Ajinomoto Build-Up Film
John Lau, Unimicron Technology Corp. (Channing Yang; John Lau; Gary Chen; Jones Huang; Ning Liu; TJ Tseng)
Printed Microstrip Interconnects for Improved RF Performance in mm-Wave Packaging
Mike Dean, Optomec