Symposium Program
Conference
October 3 - 6, 2022
Exhibition
October 4, 2022 | 11am-4pm
October 5, 2022 | 11am-6:30pm
Professional Development Courses
October 3, 2022
IMAPS 2022 is being held at:
Hynes Convention Center
900 Boylston St
Boston, MA 02115
IMAPS is pleased to announce the technical program for IMAPS 2022. The program includes keynote presentations, Professional Development Courses, technical presentations and Posters. New this year -- Monday will also feature a co-located Workshop on STRATEGIES TO REVITALIZE THE ON-SHORE PACKAGING AND ASSEMBLY DEFENSE INDUSTRIAL BASE. Learn more below!
MONDAY, OCTOBER 3
Professional Development Courses (PDCs) & the co-located Workshop on ON-SHORING
All times listed as Eastern Time
Attendees can select/register for ONE PDC during each of the timeslots below.
| PDC AM1: Introduction to Fan-Out Wafer Level Packaging (FOWLP) - Beth Keser, Director, Intel Corp. | PDC AM2: Semiconductors in Automotive - Technology Trends and Reliability - Vikas Gupta, ASE & Pradeep Lall, Auburn University | PDC AM3: Flip Chip Tech - Mark Gerber, ASE US, Inc. |
PDC Coffee Break in Foyer
| PDC AM4: Chiplet Design and Heterogeneous Integration Packaging - John Lau, Professor, Unimicron Technology Corp. | PDC AM5: Wire Bond Process Development and Optimization - Henri Seppanen, Research Scientist, Kulicke & Soffa Industries & Aashish Shah, Principal Engineer and Technical Lead, Kulicke & Soffa Industries | PDC AM6: Chip Packaging Processes and Materials - Syed Ahmad, Director, City of Jamestown, ND |
PDC "Box Lunch" for those taking morning & afternoon classes
| PDC PM1: Fan Out for Advanced Packaging Applications - John Hunt, Senior Advisor & Jan Vardaman, President, TechSearch International, Inc. | PDC PM2: System-in-Package (SiP) - System Solutions Through Miniaturization - Mark Gerber, ASE US, Inc. | PDC PM3: Fundamentals of Thermal Management - Rita Mohanty, Sr. Scientific Principal, Henkel Corp. |
PDC Coffee Break in Foyer
| PDC PM4: Polymers for Wafer Level Packaging - Jeffrey Gotro, President, InnoCentrix, LLC | PDC PM5: 3D Flip Chip Package Technology and Assembly Processes - Tom Dory, R&D Manager, Fujifilm Electronic Materials | CANCELLED - PDC PM6: Qualification Formalism for Markets Demanding High Quality & Reliability Standards - Shubhada Sahasrabudhe, Principal Engineer, Corporate, Intel Corp. & Shalabh Tandon, Sr. Director Corporate Quality Network, Intel Corp. |
5:30 pm – 7:00 pm
Sponsored by:
WELCOME RECEPTION
(Hynes Convention Center 2nd Floor Boylston Hallway)
Open to all IMAPS 2022 & On-shoring Workshop participants
7:00 pm – 8:00 pm
Sponsored by:
IMAPS DEI TOWNHALL DISCUSSION and RECEPTION:
EQUITY vs. EQUALITY IN THE WORKPLACE
(Hynes Convention Center Room 210)
Chair: Robin Davis, Deca Technologies
Committee: Erica Folk, Northrop Grumman; Beth Keser, Intel;
Dan Krueger, Honeywell; Urmi Ray, iNEMI; Nicole Wongk, Honeywell
This will be a one-hour townhall – open discussion and panel format. Join us for open and lively conversation around many important topics for all to consider in today’s challenging work environment, including the important differences between equity and equality in the workplace.
PANELISTS:
KT Moore, Cadence Design Systems - VP Corporate Marketing
Shelby Nelson, Mosaic Microsystems – Chief Technical Officer
Urmi Ray, Saras Micro Devices – Chief Technology Officer
Jean Trewhella, GlobalFoundries - Director of PostFab New Product Introduction
Susan Trulli, Raytheon Technologies, RMD Advanced Microelectronics Solutions | Principal Engineering Fellow
Food & Drink Provided
TUESDAY, OCTOBER 4
7:30 am - 8:30 am
Sponsored by:
BREAKFAST & COFFEE IN FOYER
(Hynes Convention Center Foyer 302-304-306)
8:30 am - 11:30 am
Sponsored by:
Opening Plenary Session, Business Meeting, Awards & Keynotes
(Hynes Convention Center 302-304-306)
9:00 am - 9:45 am (Hynes Convention Center 302-304-306)
KEYNOTE 1: ELECTRONIC-PHOTONIC PACKAGE INTEGRATION
The traditional microelectronic focus on performance scaling under constant cost and energy envelopes was based on transistor dimensional scaling. A technology transition to the new scaling vector of chips-per-package is being driven by two primary needs: i) heterogeneous integration of special purpose processors, accelerators and ASICs for functionality and energy efficiency; and ii) photonic integration for I/O bandwidth and reach. Construction of AI platforms for autonomous vehicles and system design optimization require scaling at functional levels to collect data, train models, simulate/recognize environments and actuate responses.
While global coordination of architecture, software and hardware advances are required, the near term bottleneck is clearly chiplet packaging. The package platforms of the past are rapidly becoming inadequate as thermal interfaces, Cu traces, and chip carrier interconnects have reached physical limits. Integration of test and assembly into package design is critical to reaching commercially acceptable cost targets. Co-Packaged Optics has already displaced a nascent On-Board Optics technology to provide system connectivity for data center systems. Professor Kimerling will describe the Roadmap vision for Interconnection 2035 and the Test, Assembly and Package advances in infrastructure, tools and performance that will enable that vision.
Development. He has authored more than 600 technical articles and more than 75 patents in the fields of integrated photonics and semiconductor processing. The Microphotonics Center Industry Consortium oversees more than 300 industrial, academic and government organizations that contribute to the Integrated Photonics System Roadmap, International (IPSR-I) releases. Kimerling was President, TMS; Chairman, Editorial Board of the Journal of Electronic Materials; and he has served on the Advisory Board, National Center for Photovoltaics, DOE and the National Materials Advisory Board, NRC. He is the recipient of the 1995 Electronics Division Award of the Electrochemical Society and the 1999 John Bardeen Award of TMS. He is a Fellow of the American Physical Society, the AAAS, TMS, MRS, Optica and the School of Engineering, UTokyo. His research teams have enabled longlived telecommunications lasers, developed semiconductor diagnostic methods such as DLTS, SEM-EBIC and RF-PCD, and pioneered silicon microphotonics.
9:45 am - 10:15 am
COFFEE BREAK IN FOYER
(Hynes Convention Center Foyer 302-304-306)
10:15 am - 11:00 am (Hynes Convention Center 302-304-306)
KEYNOTE 2: AUTOMOTIVE MEMS: OVERVIEW, DEVELOPMENTS AND INNOVATIONS
MEMS based sensors are key-enabler in a wide range of automotive applications, proliferation of autonomous driving systems further enhancing their importance: inertial sensors with highest performance are critical, in order to provide continuous robust system operation. Especially, as frequent driving situations occur, where access to other data gathering means is interrupted.
Such use-cases greatly benefit from increased performance of different sensor parameters. Therefore, innovations are needed across all engineering domains, from system architecture to packaging, constantly pushing the boundaries. In his presentation, Dr. Ando Feyh (MEMS Strategy Management, New Business and M&A), will share some insights and cover recent developments in the field of MEMS based sensors. Focus will be on the processing side, as well as on the packaging side, and show their resulting impact on further improving sensor performance. He will also provide an overview on the evolution of packaging technology with focus on automotive applications with outlook on upcoming innovations.
MEMS Strategy Management, New Business and M&A
Ando Feyh received his PhD degree in Electrical Engineering at RWTH Aachen University after a Physics Diploma degree at Stuttgart University.
He started his career at Bosch in 2002 within Corporate Research and Advance Engineering. Concentrating in the field of microsystems, he worked on integration and miniaturization of MEMS sensors, in development and in project management positions.
Between 2010 and 2014 he was an expat in the Silicon Valley in Palo Alto, leading different MEMS projects and an engineering group. 2014 he joined the Bosch internal IoT startup Bosch Connected Devices and Solutions, first responsible for the Advance Engineering and System Architecture group, later as Head of Engineering. Mid 2018 he was nominated Head of Technical Responsibility / CTO, responsible for engineering, project management and product management of IoT devices. Since mid 2021 he is focusing on MEMS Strategy Management, New Business and M&A projects within the Automotive Electronics sensor division.
11:15 am - 1:15 pm
Sponsored by:
NETWORKING AND LUNCH IN EXHIBIT HALL C
A – SiP / Design / Manufacturing Optimization Track Chairs: Dongshun Bai, Brewer Science; Bora Baloglu, Amkor Technology; Fang Luo, Stony Brook University | B - Wafer Level/Panel Level (Advanced RDL) Track Chairs: | C -High Performance-High Reliability Track Chairs: | D - Advanced Packaging (Flip Chip/2.5D/3D/Optical) Track Chairs: | E - Advanced Process & Materials (Enabling Technologies) Track Chairs: | |
| 1:15pm – 5:10pm | (Hynes Room 207) TPM1 - DESIGN, MODELING & SYSTEMS SIMULATION Session Chairs: Karthik Dhandapani, Qualcomm; Lei Fu, AMD | (Hynes Rooms 302-304-306) TPM2 - WAFER-LEVEL-FAN-OUT AND ADVANCED RDL Session Chairs: Frank Wei, Disco; Rose Guino, Henkel; Ravi Agarwal, Meta | (Hynes Room 210) TPM3 – EXTREME ENVIRONMENT Session Chairs: Zhenzhen Shen (Jenny), Reality Labs (Meta Platforms, Inc.); Otto Fanini, Halliburton Energy Services | (Hynes Room 208) TPM4 – INVITED SESSION: OPTICAL CO-PACKAGING Session Chairs: Tolga Tekin, Fraunhofer IZM; Vivek Raghunathan, Xscape Photonics | (Hynes Room 209) TPM5 – ADVANCE PROCESSES AND MATERIALS Session Chairs: Aric Shorey, Menlo Microsystems; Sylvain Pharand, IBM |
| 1:15pm – 1:40pm | Simple Solution to Estimating and Predicting Transient Current in Small Signal AC Circuits Virgil Ganescu, York College of PA | Inspection Solution for 2um RDL from Wafer-Level to Panel-Level Fan-out Process Leon Lin, Onto Innovation (Anderson Liu; Jay Chen; Maruko Wu; Cheolkyu Kim; Zhuan Liu) | Towards Ultra-High Stability: MEMS Inertial Sensors Gaurav Vohra, Analog Devices (Amrit Abrol) | Electro-Optical Co-design for Future Electronic & Photonic System of Chips Architectures Kenneth Larsen, Synopsys | Novel Electroformed Ni-Au alloy for High Temperature Semiconductor Test Structures Robert Hilty, Xtalic Corporation (Jane Freydina) |
| 1:45pm – 2:10pm | An Organic Package Designer's Guide to Transitioning to FOWLP and 2.5D Design Bill Acito, Siemens EDA | Influence of Rigid Carrier Substrate and its Release Layer on Warpage of Fan-out chip last WLPs & PLPs Yoshinori Matsuura, Mitsui Mining & Smelting Co.,LTD., (Joji Fujii) | Electrically Insulative Film Adhesive with Enhanced Thermal Performance to Assemble High Power Density Electronic Device Yuan Zhao, Henkel Corporation | Electronic and Photonic Heterogeneous Integration and Fiber-Interconnection using Self-Aligning Stitch-Chip Technology Muhannad Bakir, Georgia Tech University | Optimization of Additively Manufactured Interposers for DC and RF Applications in Printed Circuit Boards Emily Lamport, University of Massachusetts Lowell (Andrew Luce; Yuri Piro; Susan Trulli; Alkim Akyurtlu) |
| 2:15pm – 2:40pm | A Comprehensive Evaluation of Al Heavy Wire Bonding and Ribbon Bonding Application in high power WBG Power Modules Yang LI, Stony Brook University (Fang Luo; Michael McKeown) | Identification of copper RDL reliability concerns related to PBO quality Terence Collier, CVInc | A Novel Lead-Free Low-Temperature Solder Paste for Wafer-Level Package Application Hongwen Zhang, Indium Corporation (Tyler Richmond) | Solder-Assisted Self-Alignment and Precision Thermode Bonding for Passive Optical Co-Packaging Hermann Oppermann, Fraunhofer IZM | Modeling the Effect of Bend Radius on the Performance of a Conformal Dual-band mmWave Patch Antenna Array Ashraf Umar, State University of New York at Binghamton (Mohamed Abdelatty, Abdullah Obeidat, Emuobosan Enakerakpo, Mohammed Alhendi, Mark Poliks)Alkim Akyurtlu) |
2:45pm – 3:40pm | BREAK IN EXHIBIT HALL C Sponsored by:
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| 3:45pm – 4:10pm | Assembly Solutions for Cost-Effective Heterogeneous Integration with Disparate Die Types Glenn Farris, Universal Instruments Corp. | Warpage and Stress Behaviors of Multiple Large Chips during Fan Out Package Process Based on Finite Element Analysis Hu Zhen, JCET (Chen Haijie; Geng Fei; Xu Hong; Guo Liang; Wang Hong; Liu Haoyu) | Advancing Reliable High-Temperature Electronics through Compatible Material Interfaces Jacob Kupernik, Ozark Integrated Circuits, Inc. (Matt Bakowski; Nick Chiolino; Matt Barlow; A.M. Francis) | Optical, Photonic and Quantum Integration in Hyperscale Data Centres of the Future Richard Pitwon, Seagate | The Science of Adhesion Insights to Understanding Adhesive Performance Doug Katze, Henkel Corporation (Yuan Zhao, Henkel Corp.; Rose Roberts, Brighton Science) |
| 4:15pm – 4:40pm | FEA Assisted Optimization of Bump Shear Test Method for Assessment of BEOL Mechanical Integrity and White Bump Risk Moon Soo Lee, Samsung Foundry (Min Kim; Wungwon Jung; A-Ram Kang; Myeong-soo Yeo; Shinyoung Chung; Eun-cheol Lee) | A novel hybrid method to integrate delicate MEMS components into a FOWLP Marc Dreissigacker, TU Berlin Microperipheric Center | Silicone Migration Risks and Mitigation in Thermal Materials Sanjay Misra, Henkel Corporation | Programmable Photonics: Enabling the Smart Operation of Optical Chips José Capmany, iPronics, Programmable Photonics | An Evaluation of Bath Life Effects on Photoresist Removal for Wafer Level Packaging Joel Bahena, Veeco Instruments - Precision Surface Processing (Phillip Tyler; John Taddei; Muthumanickam Sankarapandian; Jamie Prudhomme; Karthikeyan Pillai; Abdullahi Said; Christopher Carr; Dario Goldfarb; Chris Waskiewicz; Qianwen Chen) |
| 4:45pm – 5:10pm | Micro-Transfer Printing for III-V Heterogeneous Integration David Gomez, X-Celeprint (Tanya Moore; James Thostenson; Kevin Oswalt; Ron Cok; Tanya Moore; James Thostenson) | Optimization of reflow profiles and warpages for extreme extension of mass reflow JIWON SHIN, Samsung Electronics (Dong-uk Kwon) | Different HW within DC, Different Optics Elad Mentovich, nVidia | Wide process latitude, Pb-free low temperature co-fire ceramic (LTCC) Brian Laughlin, DuPont Microcircuit and Component Materials (Ahmed Salah; Russell Anderson; Young Yoon; Brad Schickling) | |
TOUR OF THE BOSTON UNIVERSITY PHOTONICS CENTER
AEMtec will provide a brief overview of their involvement at the Tech center.
Rana Gupta the head of the Tech center will talk about the work they do there.
Tours would then be given in small groups.
It’s about a twenty minute walk from Hynes to the Center.
AEMtec can provide a shuttle transportation service, if needed.
There will be a light reception - Hors d'oeuvres, beer, wine and soft drinks will be served.
IMAPS attendees interested must RSVP
Click here to RSVP and for more information
WEDNESDAY, OCTOBER 5
7:00 am - 8:00 am
Sponsored by:
BREAKFAST & COFFEE IN FOYER
(Hynes Convention Center Foyer 302-304-306)
8:00 am - 9:45 am
Sponsored by:
Day 2 Opening & Keynotes (Hynes Convention Center 302-304-306)
8:15 am - 9:00 am (Hynes Convention Center 302-304-306)
KEYNOTE 3: 6G: OPPORTUNITIES AND PACKAGING CHALLENGES
6G communication technology will be transformative to the connected world in terms of bandwidth, delivering on the promise of truly ubiquitous connectivity and a better balance of compute/connect options. But, with great opportunity come great challenges. With regards to semiconductor packaging, the challenges of signal integrity, thermal management, and integration/miniaturization are clearly in scope with effective solutions needed.
Vice President, Package Innovation
Glenn G. Daves is Vice President of Package Innovation at NXP Semiconductors. He is responsible for package design, package technology development, and assembly process development in support of NXP’s full product portfolio. Prior to its acquisition by NXP, Glenn led packaging and printed circuit board development for Freescale Semiconductor. Prior to that, he led global packaging product and technology development at the IBM Corporation. He has also held leadership positions in project management, test and burn-in engineering, and assembly manufacturing engineering. Glenn holds twenty-seven U.S. patents and has degrees from Brown University, the University of Illinois at Urbana-Champaign, and Alliance Theological Seminary. He serves on the board of trustees of Nyack College and on the National Leadership Council of World Vision U.S.
9:00 am - 9:45 am (Hynes Convention Center 302-304-306)
KEYNOTE 4: CHANGING DYNAMICS OF THE SEMICONDUCTOR GLOBAL SUPPLY CHAIN AND SCOPE, OPPORTUNITIES FOR INDIA
Semiconductors are ubiquitous and found in all electronic devices from kids toys to household appliances to automotive to fighter jets. No matter it's called new oil which is essential for digital economy and green world and all major countries want to have it in their backyard, in order to have secure supply chain. In last couple of years, shortage of semiconductors induced by the disruption of supply chain due to COVID-19 and US-China trade war, has amplified the supply chain dependency on few countries and bring it in common public domain. Taiwan, Korea and China accounted for >85% of global foundry revenue last year. The major economies across the world have understood the strategic importance of semiconductor and passed legislation to support local manufacturing by providing generous incentives. On-shoring is the new trend, which will change the semiconductor supply chain landscape in next 5-10 years.
The presentation will focus on the changing dynamics of semiconductor global supply chain and how emerging economies like India can emerge the next destination of semiconductor manufacturing especially in the backend /OSATs segment. Further, the pros and cons of offshoring, it's sustainability and effectiveness will be discussed.
Vice President and Head, BD Semiconductor Manufacturing
Santosh Kumar is currently VP and Head, BD Semiconductor Manufacturing at Reliance. Previously, he worked as Senior Director at Yole Développement for advanced packaging. He is involved in the market, technology and strategic analysis of the microelectronic assembly and packaging technologies. He worked on multiple projects with top semiconductor companies including material and equipment suppliers. His main interest areas are advanced IC packaging technology, equipment & materials. He is the author of several reports on fan-out / fan-in WLP, flip chip, and 3D/2.5D packaging. He received the bachelor and master’s degree in engineering from the Indian Institute of Technology (IIT), Roorkee and University of Seoul respectively. He has published more than 40 papers in peer reviewed journals and has obtained 2 patents. He has presented and given talks at numerous conferences and technical symposiums related to advanced microelectronics packaging.
9:45 am - 10:15 am
COFFEE BREAK IN FOYER
(Hynes Convention Center Foyer 302-304-306)
| 10:15am – 12:10pm | (Hynes Room 207) WAM1 - ADVANCED MATERIALS Session Chairs: Luke Prenger, Brewer Science; | (Hynes Rooms 302-304-306) WAM2 - FAN-OUT RDL AND ASSEMBLY PROCESSES Session Chairs: Li-san Chan, Heraeus; | (Hynes Room 210) WAM3 – HIGH RELIABILITY Session Chairs: Vikram Venkatdri, Analog Devices; Irene Popova, Ancosys | (Hynes Room 208) WAM4 - INTERCONNECTS Session Chairs: Lyndon Larson, DuPont Electronics | (Hynes Room 209) WAM5 – POWER SUBSTRATE TECHNOLOGY Session Chairs: Doug Hopkins, North Carolina State University; Doug Shelton, Canon USA |
| 10:15am – 10:40am | A Drop-in High-Temperature Lead-Free Solder Paste that Outperforms High-Pb Pastes in Power Discrete Applications Hongwen Zhang, Indium Corporation (Tyler Richmond) | Assembly Technology for FO-MCM with HBM in HPC Application Shuai-Lin (Bradley) Liu, SPIL (Nicholas Kao; George Pan; David Lai; Yu-Po Wang) | Electromigration Risk Assessment and Circuit Optimization using Innovative Multiphysics Modeling Chongyang Cai, Google (zhi yang; Yuan Li; Padam Jain; Terry Kang) | Investigation of electroless copper plating with high plating coverage in small BVH for next generation fine pattern SAP Richard DePoto, C. Uyemura & Co., Ltd. (Shinichiro Yoshida, Tomoharu Nakayama; Hisamitsu Yamamoto) | Solid-State Ultra-Thin Bondlines Between CTE-Mismatched Silicon and Aluminum |
| 10:45am – 11:10am | Development of a Photopolymer-Based Dielectric Nanocomposite for High Resolution Direct-Write Processes Yuri Piro, University of Massachusetts (Christopher Aerias; Andrew Luce; Emily Lamport; Yibo Li; Susan Trulli; Alkim Akyurtlu) | Maskless direct write lithography for 3D wafer-level-system-integration Frank Windrich, Fraunhofer IZM-ASSID (Achim Jehle; Sven Preuss) | On Excess CO2 within a Hermetically Sealed 14-Pin Butterfly Package: Solubility of CO2 within Fluorocarbon Liquids Mark De Luna, Northrop Grumman (Todd Uramoto) | Microstructural Characterization of Sn57Bi1Ag Solder Alloy Joints Sarangapani Murali, HERAEUS MATERIALS SINGAPORE PTE LTD (Evonne Lim Yee Weon; Miew Wan Lo; Abito Bayaras Danila; Yee Ting Lo; Loke Chee Keong; Kang SS Sungsig) | A New Look for SiC! |
| 11:15am – 11:40am | Advancements, Versatility, and Flexibility of Dual-Layer Material System for Advanced Packaging Applications Luke Prenger, Brewer Science, Inc. (Andy Jones; Dongshun Bai; Matt Koch) | Printing of Micro and Nanoscale Heterogenous Integrated and Advanced Electronics Packaging Ahmed Busnaina, Nano OPS, Inc. | A Physics-of-Failure Investigation into Flip Chip Reliability Based on Lead Free Solder Fatigue Modeling Sean Brinlee, CAES | A high-uniformity, high-purity copper pillar ECP process with limited acid concentration Pingping Ye, MacdermidAlpha (Adam Letize; Jianwen Han; Stephan Braye; Ashley Kuppersmith; Kyle Whitten; Thomas Richardson; Elie Najjar) | Understanding Criticality of Thermal Performance in Thermal Interface Material Applications |
| 11:45am – 12:10pm | TAT PCB for High Frequency Electronics James Lin, Corning (Geriant Owen; Timothy Orsley) | Development of all new structure of Dicing Die Attach Film (DDAF) for Stealth Dicing and Cool Expansion processes Wataru Iwaya, LINTEC OF AMERICA, INC. (Yosuke Sato; Misaki Sakamoto; Masanori Yamagishi; Naoya Saiki) | Simulation and Experimental Study on Edge Bonding Shape for BGA Packages with High Reliability Yasuhiko Kato, Showa Denko (Hiroyuki Hamagami; Tomoaki Shibata; Kohei Seki; Ryota Sato) | Dielectric Property Effect with Dielectric Constant for Millimeter Wave Antenna Design Chih Yuan Shih, Teny (Chia Chu Lai; Yu-Po Wang) | Interfacial Diffusion Mechanism between ALD Al2O3 passivation/Cu in Direct Bonded Copper Substrate for Power Electronics |
12:15 pm - 1:30 pm
NETWORKING & LUNCH IN EXHIBIT HALL C
| 1:30pm – 5:25pm | (Hynes Room 207) WPM1 - ADVANCED PACKAGING & RELIABILITY Session Chairs: Sunny Agarwal, ITW EAE; Varughese Mathew, NXP Semiconductors | (Hynes Rooms 302-304-306) WPM2 – WAFER LEVEL CHIP SCALE PACKAGING AND ADVANCED MATERIALS Session Chairs: SooSan Park, JCET; | (Hynes Room 210) WPM3 – INVITED SESSION: HETEROGENEOUS INTEGRATION ROADMAP Session Chairs: Bill Chen, ASE Group; Benson Chan, Binghamton University | (Hynes Room 208) WPM4 – FLIP CHIP Session Chairs: Karl Freidrich Becker, Fraunhofer IZM Jim Will, SkyWater Technology | (Hynes Room 209) WPM5 – WIRE BONDING Session Chairs: Martin Schneider-Ramelow, Fraunhofer IZM; Mike McKeown Hesse Mechatronics |
| 1:30pm – 1:55pm | Board Level Reliability of Flipchip Package Nishant Lakhera, NXP Semiconductors (Andrew Mawer; Mollie Benson) | Novel Temporary Bonding Film Adapted to Xenon Flash Lamp De-bonding System for FOWLP Application Tomoaki Shibata, Showa Denko (Yuta Akasu; Shogo Sobue; Ayaka Kuroda; Saeko Ogawa) | Heterogeneous Integration Roadmap Overview Bill Chen, ASE Group | Pre-applied underfill Technique for Fine-pitch Cu Pillar 3D Die Stacking to Enable 2.5/3D Advanced Packaging Nicholas Lay, Northrop Grumman Corp (Kaysar Rahim; Melissa Holliday; Nicholas Dinapoli) | High Robustness of Coated-Ag Wire Bonding Sarangapani Murali, Heraeus Materials Singapore Pte Ltd (Evonne Lim Yee Weon; Dhayalan Mariayppan; Miew Wan Lo; Joanne Chong Mei Hoe; Senthilkumar Balasubramanian; Kang SS Sungsig) |
| 2:00pm – 2:25pm | Investigation of CuAl IMCs Corrosion in Chloride Environment and its Prevention Strategy John Alptekin, University of North Texas (Eswar Gopalakrishnan; Dinesh Kumar Kumaravel; Kevin Antony; Oliver Chyan; Varughese Mathew) | Protected Wafer Level Chip Scale Packaging (P-WLCSP) Douglas Hackler, American Semiconductor, Inc. (Ed Prack; Randall Parker) | Single & Muti-chip Integration Benson Chan, Binghamton University | Optimization of the Microstructure for Copper-to-Copper Direct Bonding by Electrodeposition Processes Ralf Schmidt, Atotech Deutschland GmbH | Insulated, Passivated & Adhesively-Promoted Bond Wire Using All-in-One Al2O3 Coating Soojae Park, Samsung Electronics Company |
| 2:30pm – 2:55pm | A Closed Form Method Combined with the Steinberg’s Solution to Estimate Number of Fatigue Cycles for Lead-Free Solders Tuan Nguyen, Raytheon Technologies | Reconfigurable NEMS based Advance packaging for Anti Reverse engineering and counterfeiting Aslam A. Khan, Aslam (Keon Sahebkar; Ryan F Need; Mark Tehranipoor; Navid Asadizanjani) | 5G Communication & Beyond Tim Lee, Boeing Research | Impact of FCBGA substrate stack-up on BLR performance Jaimal Williamson, Texas Instruments (Yutaka Suzuki; Ron Eller) | Digital Twins and Smart Manufacturing for Wire Bonding Basil Milton, Kulicke & Soffa Industries, Inc. (Ray Cathcart; Odal Kwon; Pavel Shusharin; Ivy Qin) |
| 3:00pm – 3:55pm | BREAK IN EXHIBIT HALL C Sponsored by: | ||||
| 4:00pm – 4:25pm | Die-embedded packaging using Corning multi-layered glass Hyung-Soo (Alex) Moon, Corning Technology Center Korea (Yu Xiao; Jong-Min Yook; Hyun-Je Chang; Hyung-Soo Moon) | Prevention of Cu electrolytic migration defects on RDL by a Cu-selective passivation to enhance reliability Ashish Shivaji Salunke, University of North Texas (Kaushik Akula; Subiksha Jayakumar; Shaurya Kumar; John Alptekin; Oliver Chyan; Ninad Shahane) | Aerospace & Defense Tim Lee, Boeing Research | Electroplated Aluminum Pillars for Ultrasonic Flip Chip Bonding Silvia Braun, Fraunhofer ENAS (Imants Cirulis; Jan Erik Liedtke; Karla Hiller; Maik Wiemer; Harald Kuhn) | Metal Oxide Removal Using Atmospheric Pressure Plasma Technology For Electronic Applications Daphne Pappas, Plasmatreat USA (Andrew Sy; Ryan Robinson; Richard Burke) |
| 4:30pm – 4:55pm | Glass Substrate for Co-Packaged Optics Lars Brusberg, Corning Research & Development Corporation (Ekin Kocabas; Jason Grenier; Lucas Yeary) | New Photo-Definable Polyimide with High Aspect Ratio Pattern Capability Masao Tomikawa, Toray Industries (Keigo Kato; Yoshiko Tatsuta; Kazuyuki Matsumura; Akira Shimada) | MEMS & Sensor Integration Michael Flaherty, Analog Devices | Chiplet Integration by Die-to-Die Pillar-Suspended BridgeIchiro Kohno, Tokyo Institute of Technology (Yoichiro Kurita, Shinji Wakisaka, Toshiaki Hirota, Takashi Saitou, Ken Ukawa) | Atomic Mechanism for Ultrasonic Wire Bonding Henri Seppanen, Kulicke & Soffa Industries (Milad Khajehvand; Panthea Sepehrband; Peter Klaerner) |
| 5:00pm – 5:25pm | Development of high performance flip chip ball grid array (FCBGA) packages for automotive application processors Gaurav Sharma, NXP Semiconductors | Glass in wafer- and panel- level packaging: On the route towards industrialization. M. Letz, Schott AG (Tobias Gotschke; Bernd Hoppe; Fabian Wagner; Ulrich Peuchert; David Vanderpool) | Automotive Vikas Gupta, ASE Group | The Effects of Voids on Solder Joint Reliability in First Level Interconnect Sze Pei Lim, Indium Corp. | Algorithm for Ultrasonic Wire Bond Outlier Classification Pedro Villa, Kulicke&Soffa (Henri Seppaenen) |
5:30 pm - 6:30 pm
sponsored by:
HAPPY HOUR IN EXHIBIT HALL C
Microelectronics Foundation Silent Auction Closes: 6:15pm
PANEL SESSION:
DEVELOPING NEXT GENERATION MMWAVE PACKAGES: WHAT DO WE NEED?
(Hynes Convention Center 302-304-306)
While 5G handset sales continue to increase, the slow rollout the 5G infrastructure continues. Over the next few years, the 5G rollout will be complete, but at the same time the industry is starting to discuss the requirements for 6G. There are already concerns about material requirements, antennal design, assembly, and test. Packages that can handle the higher frequencies are anticipated for mobile devices, small cells, infrastructure, automotive, and defense. What frequencies are being targeted in each of these areas and what should the focus be for package development? Are there areas that the industry ecosystem should address? With the promise of 5G, and eventually 6G, more data will be collected, stored, and shared. Will our current datacenter structure support all the processing of the increased data expected with 5G and 6G? What new package developments are required? This panel of experts will discuss the development of next generation packages and needs to be addressed.
Moderators:
Jan Vardaman, TechSearch International; Susan Bagen, Consultant
Glenn Daves, NXP Semicondoctors | VP, Package Innovation
Mark Gerber, ASE Group | Sr. Director Engineering and Technical Marketing
THURSDAY, OCTOBER 6
7:00 am - 8:00 am
Sponsored by:
BREAKFAST & COFFEE IN FOYER
(Hynes Convention Center Foyer 302-304-306)
8:00 am - 9:00 am
Sponsored by:
8:15 am - 9:00 am (Hynes Convention Center 302-304-306)
KEYNOTE 5: ADVANCING MEDICAL ELECTORNICS AT THE INTELLIGENT EDGE
Sensing and computing at the Intelligent Edge will drive the next big wave of growth in the semiconductor industry as a trillion sensors are deployed to gather data from everywhere and everything. The data generated from ubiquitous electronics will overwhelm the Cloud and we will be forced to make many decisions at the Intelligent Edge. The health care industry will not be immune. In fact, it will demand it. As our population ages, demand for health care services is overwhelming conventional solutions and exploding costs. One innovative solution is to move from a reactive to preventative approach minimizing hospital admittance and readmittance. Monitoring, diagnosing, and even treating patients outside of an acute hospital setting, and even at home, is the Intelligent Edge. Let’s explore how innovations in packaging will help enable this future.
David Bolognia, ADI Fellow, Packaging Technology
David Bolognia joined Analog Devices in 2011 charged with the task of building a team and necessary capabilities required to grow System in Package into a mainstream packaging technology at ADI in support of applications in RF, medical imaging, digital health care and others. In recent years, David has focused on the mechanical development of ADI’s highly integrated products in digital health care applications. Previously, David was a Vice President at Amkor Technology leading the System in Package BU and worked in product design and development of computer products at Compaq Computer. He started his career in the petrochemical industry in Houston, TX after graduating from Rice University with a BSME.
9:00 am - 9:30 am
COFFEE BREAK IN FOYER
(Hynes Convention Center Foyer 302-304-306)
| 9:30am – 11:25am | (Hynes Room 207) THAM1 - MANUFACTURING / PROCESS OPTIMIZATION Session Chairs: Santosh Kudtarkar, Analog Devices; Amol Deshpande, Wolfspeed | (Hynes Rooms 302-304-306) THAM2 - MANUFACTURING CONSIDERATIONS Session Chairs: Vivek Dutta, Mitsui Mining & Smelting Co. Ltd.; Gengxin Zhang, Meta Platform Inc. | (Hynes Room 210) THAM3 – HIGH POWER Session Chairs: Konstantin Yamnitskiy, Medtronic; Jeff Leal, Mycronic | (Hynes Room 208) THAM4 – HETEROGENEOUS INTEGRATION Session Chairs: Arsalan Alam, UCLA CHIPS / AMD; Manish Dubey, AMD | (Hynes Room 209) THAM5 - NOVEL INTERCONNECT METHODS Session Chairs: Jeff Gotro, Innocentrix; Kevin Demartini, DuPont |
| 9:30am – 9:55am | Additive Packaging for Bare Die and Additively Integrated Antenna Christopher Areias, University of Massachusetts Lowell (Emily Lamport; Yuri Piro; Alkim Akyurtlu) | Design of Wafer Level Solder Seals - A Surface Energy Perspective Thomas F. Marinis, Charles Stark Draper Laboratory (Joseph W. Soucy) | Thermal Performance of Liquid Metal Paste Containing low Content of Metal Particles for Thermal Interface Materials Jeff Kurish, Indium Corp. (Guangyu Fan) | Using ADKs to enable early-stage chiplet-to-chiplet interface compliance John Park, Cadence Design Systems, Inc. (Ken Willis) | A Hybrid Pressure-less Silver Sintering Technology for High-power Density Electronics Yuan Zhao, Henkel Corporation (Bruno Tolla; Douglas Katze) |
| 10:00am – 10:25am | Innovations in Soldering Materials and Optimization of Solder Paste Printing and Inspection Parameters for System-in-Package Assembly Evan Griffith, Indium Corporation (Casey Rowland; David Sbiroli; Jonas Sjoberg) | Fabrication of Panel-Level Glass Substrates with Complete Design Freedom using LIDE Rafael Santos, LPKF Laser & Electronics (Nils Anspach; Norbert Ambrosius; Stephan Schmidt; Roman Ostholt) | Double Sided Integrated GaN Power Module with Double Pulse Test (DPT) Verification Sourish S Sinha, North Carolina State University (Tzu-Hsuan Cheng; Douglas C Hopkins) | Status and Outlooks of 2.3D IC Integration John Lau, Unimicron | Study for Bonding Technology by Electroplated Nano porous Cu Structure Daiki Furuyama, Mitsubishi Materials corporation (Takuma Nakagawa; Junta Inoue; Koji Tatsumi; Sho Nakagawa; Takuma Katase) |
| 10:30am – 10:55am | Direct-Write Printed Wearable Metasurfaces Adria Kajenski, University of Massachusetts Lowell (Shahriar Khushrushahi; Guinevere Strack; Alkim Akyurtlu) | A novel analytical method of Thallium determination in gold electrodeposition Jingjing Wang, ECI Technology (Patrick Saitta; Eugene Shalyt) | Design to cost Ag free silicon nitride AMB substrate for automotive power module applications Habib Mustain, Heraeus Electronics (André Schwöbel; Benjamin Fabian; Daniel Schnee; Anton Miric) | Glass interposers with through-glass vias for heterogeneous integration Shelby Nelson, Mosaic Microsystems | Time to Failure due to Current Stressing of SnBi-based Solder Joints Eric Cotts, SUNY Binghamton (Faramarz Hadian; Javier Flores; Sitaram Panta) |
| 11:00am – 11:25am | Finding a Happy Medium for Heterogeneous Cache Integration using M-Series Fan-out Technology Benedict San Jose, Deca Technologies, Inc (Robin Davis; Tim Olson) | Study on CPI behaviors of X Dimension Fan-Out Integration (XDFOI) packages Nokibul Islam, JCET (Chen Haijie; Hu Zheng; Wang Chen; Pan Hao; Xu Li; He Ming; Xie Jielei) | Smaller than MLCC: CCW (Ceramic Capacitor Wire) Soojae Park, Samsung Electronics Company | Heterogeneous Integration Hybrid Substrate with Ajinomoto Build-Up Film John Lau, Unimicron Technology Corp. (Channing Yang; Gary Chen; Jones Huang; Ning Liu; TJ Tseng) | Printed Microstrip Interconnects for Improved RF Performance in mm-Wave Packaging Justin Bourassa, Optomec |
POSTERS & PIZZA
Interactive Poster Session & Pizza Luncheon
(Hynes Convention Center 3rd Floor Boylston Hallway)
Erica Folk, Northrop Grumman; Jon Aday, Amkor Technology
Open-Cavity Plastic Packages: A Robust Solution for High-Reliability Applications
Sam Sadri, QP Technologies (Tom Tammen)
New Packaging Technology for 2-dimensional VCSEL Arrays and Their Electro-Optical Performance and Applications
Rainer Dohle, Micro Systems Technologies (Maximilian Wallrodt; Gerold Henning; Cristoph Greus; Christian Neumeyr; Juergen Rosskopf; Robert Hohenleitner)
Heterogeneous Integration of III-V Lasers in a 300mm CMOS Manufacturing Line
Sarah Baranowski, The Research Foundation for State University of New York (Anh Nguyen; Seth Kruger; Lewis G Carpenter; Amit Dikshit; Colin McDonough; David L Harame)
Development of high throughput solderable surface mount free space optical interconnect module for co-packaged processor
Venkata Ramana Pamidighantam, LightSpeed Photonics (Rohin Kumar Yeluripati)
Development of robust sensor packages for autonomous underwater vehicles
Karl-Friedrich Becker, Fraunhofer IZM (Marcus Voitel; David Schütze; Thanh Duy; Malte Spanier; Ole Hoelck; Martin Schneider-Ramelow)
Current Trends and Challenges in Vertical Optical Interconnects
Drew Weninger, Massachusetts Institute of Technology (Samuel Serna Otalvaro; Lionel Kimerling; Anuradha Agarwal)
Novel Micro-Textured Film Offers Promise in Universal Handling of 3D Devices
Raj Varma, Delphon
Mixed reaction gold as versatile plating solution for ENIG, ENEPIG and EPAG plating
Jobert van Eisden, Atotech Deutschland GmbH (Britta Schafsteller, Mario Rosin, Timo Schlosser, Gustavo Ramos)
ROADMAP TO COST-EFFECTIVE SILICON SCALING: THE HETEROGENEOUS INTEGRATION
Roberto Antonicelli, JCET Group
Thick-film - a mature technology at the cutting edge of advances in the electronics industry
Gregg Berube, Heraeus
Thermal Performance of Liquid Metal Paste Containing low Content of Metal Particles for Thermal Interface Materials
Jeff Kurish, Indium Corp. (Guangyu Fan)
Also presenting in session THAM3 High Power
Board Level Reliability of lead-frame based substrate and surface finishing technology
In-Seob Bae, Haesung DS
The Study of Highest Thickness Photo Resist for Cu Post of Fan-Out Wafer Level Packaging
Yuseon Heo, Samsung Electronics (Jiyoung Lee, Jieun Park, Junhyeong Park, Jihye Shimada, Sueryeon Kim)
Chiplet Integration by Die-to-Die Pillar-Suspended Bridge
Yoichiro Kurita, Kyo Institute of Technology (Ichiro Kohno, Shinji Wakisaka, Toshiaki Hirota, Takashi Saitou, Ken Ukawa)
Also presenting in session WPM4 Flip Chip
Advanced optical packaging for medical, telecommunication, industrial and semiconductor applications
Daniel Lieske, AEMtec GmbH
Component out of Pocket (COOP)
Craig Blanchette, BAE Systems
Modeling the effect of hatched grounds on the radio-frequency performance for
Aerosol Jet silver ink on Kapton substrate
Mohamed Abdelatty, State University of New York at Binghamton
(Ashraf Umar, Abdullah Obeidat, Emuobosan Enakerakpo, Mohammed Alhendi, Mark Poliks)
Microfabrication and Packaging of 3D Through Silicon Via Inductors
Bruce Kim, City University of New York
POST-EVENT FUN! GOLF, LAB TOURS, ETC
IMAPS GOLF OUTING – FOUNDATION FUNDRAISER
1:00pm Scramble Format
Newton Commonwealth Golf Course
$100/golfer includes golf, cart, lunch (club rentals additional)
Mulligans, Putting Strings, Prize Holes (Closest to Pin & Longest Drive)
MIT.nano Lab Tour
2:00pm Start
Open to all IMAPS attendees.
RSVP NOW CLOSED -- before October 4 at 12pm eastern
IMAPS participants will show up at the entrance of the Lisa Su building (MIT.nano building 12) at 2 pm on 10/6. Here is an interactive map of the MIT campus. Visit the MIT.nano building which includes a Class 100 Cleanroom and a Lab for Education and Application Prototypes (LEAP) for electronic-photonic chip packaging. Contact: Anu Agarwal at 781 771 7305 (anu@mit.edu).