Symposium PDCs


Registrations for PDCs are no longer being accepted. PDCs were offered during live event hours only, and are not available for replay or on-demand. Please join us at the International Conference on Device Packaging in April for the next day of instruction by the best teachers in the industry!

What are PDCs?

Professional Development Courses are supplemental two-hour classroom-style tutorials with a narrow educational focus taught by the best in the industry. The topics offered at IMAPS 2020 are designed to help attendees broaden their scope of knowledge.

Virtual Delivery

PDCs will be taught in a real-time, live atmosphere in a private zoom room between the instructor and course registrants. Questions will be taken in an interactive environment.

Each course will be taught during it's published date and time only. PDCs will not be available on-demand. Attendees agree and understand that their registration is for a real-time instructional course.

IMAPS 2020 PDC Course Offerings

NEW! The 2020 PDC courses are offered each day of the virtual symposium, including prior to the conference on Friday, October 2nd. Attendees must register for each course as an add-on to their overall symposium registration. Attendees may select up to one course in each time slot. 

Make sure to review your preferred course's date and time slot before registration. Course fees are non-refundable.


Course Fees and Inclusions

Course Fees: $250 per course.

Fees include access to the 2-hour course led by reputable industry leaders.
These fees are non-refundable but may be transferred to another registrant prior to the start of the course. No transfers will be accepted once the course has begun. Click here to view the full attendee terms and conditions.

How to Register

  1. Click here to get started.
  2. Log into your member account or create a guest* account.
    *Remember! Member, Nonmember, Speaker, Chair, and Student event registrations include a one-year IMAPS membership. Make sure to populate your account thoroughly. Guest accounts will be converted to member accounts within 30 days of your event registration.
  3. Select the IMAPS 2020 event. 
  4. Select your overall conference registration type (Member, Nonmember, Speaker, Chair, Student).
    Only planning to attend a PDC? Select "PDC Only" as your registration type. PDC-only registrants will not have access to additional conference content. 
  5. Choose your course(s) selection in the time slot drop-down boxes. Select up to one course per time slot.
  6. Check out. You will receive a confirmation email detailing your registration. 

If you need to add or change course selection(s) after completing a registration, please contact Shelby Moirano at 

Course Descriptions

Course A3:
5G/mmWave Package Development Requirements and Solutions
Urmi Ray, Consultant

The fifth Generation (5G) mobile communication era is expected to address the insatiable need for data communication by introducing mmWave technology and protocols. The unprecedented latencies offered by 5G Networks will enable users to indulge in gigabit speed immersive services regardless of geographical and time dependent factors.
The key to enabling this architecture is packaging and system integration, especially involving an effective antenna structure and RFIC communication in cost-effective, small form-factor packages. As full speed development, demonstration and qualification of mmWave systems have accelerated in 2017, different design and packaging architectures are emerging. 
This PDC will provide a comprehensive landscape of package development options including LTCC, eWLB/FOWLP as well as laminate based packaging. The specific requirements of materials and process needs (low dielectric material, copper roughness requirements) are discussed. Multiple different package structures are presented as case studies to demonstrate comparative performance of eWLB vs laminate packages. Product application spaces ranging from mobile/handheld to network infrastructures and automotive/satellite radars are highlighted. Key aspects and guidelines towards a cost/performance trade-off analysis will be summarized.

Course A4:
Polymers for Electronic Packaging
Jeffrey Gotro, InnoCentrix LLC

The course will provide an overview of polymers and the important structure-property-process-performance relationships for electronic packaging.  The main learning objectives will be:
  1. Understand how polymers are used in electronic packaging
  2. Learn why specific chemistries are used depending on the application
    a. Die attach adhesives
    b. Underfills (capillary and wafer level)
    c. Epoxy mold compounds
    d. Wafer level packaging
    e. High Density Interconnect (HDI) substrates 
  3. Overview of rheology and rheological characterization of polymers in electronic applications  
Participants are invited to bring problems for discussion.

Course B4:
Heterogeneous Integrations (SiPs)
John Lau, Unimicron Technology Corporation


Heterogeneous integration uses packaging technology to integrate dissimilar chips, photonic devices, and/or components (side-by-side and/or stack) with different materials and functions, and from different fabless design houses, foundries, wafer sizes, feature sizes and companies into a system or subsystem. For the next few years, we will see more implementations of a higher level of heterogeneous integration, whether it is for time-to-market, performance, form factor, power consumption or cost. In this lecture, the introduction, recent advances, and trends in heterogeneous integrations will be presented. If you (students, engineers, and managers) are involved with any aspect of the semiconductor packaging and electronics assemblies, you should attend this course. It is equally suited for R&D professionals and scientists. All the materials are based on the papers and books published in the past 3 years.  
  1. Introduction
  2. System-on-Chip (SoC):
  3. Heterogeneous Integrations or SiPs:
  4. Heterogeneous Integrations vs. SoC.
  5. Heterogeneous Integrations on Organic Substrates:
    CPU with HMCs,
    Networking Chipset on Organic Interposer,
    2.1D IC Integration,
    Flip Chip on Board
  6. Heterogeneous Integrations on Silicon Substrates (TSV-Interposers):
    SoW (System-on-Wafer),
    CoWoS (Chip-on-Wafer-on-Substrates),
    Fabrication of TSVs,
    Fabrication of RDLs,
    Xilinx/TSMC's CoWoS,
    NVidia/TSMC's CoWoS-2,
    AMD/UMC's Graphic Cards,
    AMD/UCSB Chiplets,
    Intel Chiplets,
    TSMC Chiplets,
    UCLA Chiplets
  7. Heterogeneous Integrations on Silicon Substrates (TSV-less Interposers, e.g., Bridges):
    Intel's EMIB,
    Imec's Bridge,
    ITRI's TSH Bridge
  8. Heterogeneous Integrations on Fan-Out RDL Substrates.
  9. Heterogeneous Integrations on Ceramics Substrates.
  10. Heterogeneous Integration of PoP (package-on-package).
  11. Heterogeneous Integration of Memory Stacks.
  12. Heterogeneous Integration of Chip-to-Chip Stacks.
  13. Heterogeneous Integration of CIS (CMOS Image Sensor) and Logic Chip.
  14. Heterogeneous Integration of LED (light-emitting diode) and TSV-Interposers.
  15. Heterogeneous Integration of MEMS (microelectromechanical systems) and Logic Chip.
  16. Heterogeneous Integration of VESCL and PD. 
  17. Trends in Heterogeneous Integrations

Course A6:
Introduction to Failure Analysis in Semiconductor Package Assembly
Tom Dory, Fijufilm Electronic Materials USA

This PDC provides details on current failure analysis methods and reliability testing in package assembly.
Workshop participants will receive a detailed review of failure analysis methods and reliability testing in assembly. Quickly finding and eliminating package defects and failures due to assembly issues is critical. Package reliability directly affects manufacturing yield, time to market, product performance, customer satisfaction and cost. Many process steps and controls are needed for a high yield and reliable assembly process. A thorough understanding of product and technology reliability principles and mechanisms of failure is essential. Knowledge of defects and failure mechanisms enables a high yielding successful assembly process through material choices, package design, process optimization, and thermo-mechanical considerations. Fault isolation, failure analysis, and materials analysis play a major role in the improvement of yield and reliability. Coordination of engineers from many disciplines is needed in order to achieve high yield and reliability. Each engineer needs to understand the impact of their choices and methods on the final product. This workshop will discuss, using examples, mechanical and thermal failure mechanisms in assembly and detection methods. 
The objective of this workshop is to provide the students with an overview of the technologies, materials, and processes involved in the latest assembly failure analysis methods.

Course B6:
Fan Out Variations - Structures and Processes for Low and High Density
John Hunt, ASE US, Inc

Fan Out technology has evolved as an alternative package to meet the need for miniaturization of electronics, while also providing improved electrical interconnectivity.  Until around 2016, Fan Out was considered primarily a solution for low density packaging requirements.
The wide use of mobile and many IOT devices coming into use has driven the need for increased capability of data centers.  Fan Out technology is now in production for many of these applications.  It also enables the heterogeneous integration of die and memory with improved electrical performance and lower cost than traditional 2.5 packaging for these data center requirements. With the advent of chiplet packaging, fan out also offers a cost-effective solution for this combination of multiple die in a single package.
We will review how the integration of wafer level processing technologies and Flip Chip packaging structures have come together into recent advances in both low density and high-density Fan Out packaging. These packages are for automotive, IoT, advanced mobile and server applications. They can have higher levels of integration and sophistication than has ever been possible in the past.  A brief overview of the concept of Fan Out packaging and history of its evolution, and Fan Out developments to meet both low- and high-end applications will be included in this course.

Course A8:
The Evolution of Flip Chip Package Technology
Mark Gerber, ASE US, Inc.

This PDC course will provide a historical overview and background on the evolution of flip chip packaging as well as short market perspective on this platform. Mobile, Infrastructure, Automotive, High Reliability, Medical and High-Performance Network and Computing all rely on Flip Chip technology to enable their silicon solutions.  Although the use of new technologies such as Fan-Out hold promise for certain applications, flip chip advancements continue to challenge many new technology competitors from a price and reliability perspective and may end up driving hybrid approaches.  Interconnect structure, process flows, materials and package integration process methods for evolving Flip Chip applications will be discussed in detail. Understanding the trade-offs between the different bump structures and package platforms is key in determining the silicon device layout and the type of design rules that can be leveraged for new products. As part of this course, the assembly process details will be discussed and will include Mass Reflow, Thermo-Compression Non-Conductive Paste (TCNCP) bonding and Laser Assisted Bonding. Reliability aspects such as IMC formations and ways to address will also be covered as a key consideration for Interconnect decisions.