Symposium PDCs


What are PDCs?

Professional Development Courses are supplemental two-hour classroom-style tutorials with a narrow educational focus taught by the best in the industry. The topics offered at IMAPS 2022 are designed to help attendees broaden their scope of knowledge.

IMAPS 2022 PDC Course Offerings

The 2022 PDC courses are offered on Monday, October 3, prior to IMAPS 2022. Attendees must register for each course as an add-on to their overall symposium registration. Attendees may select up to one course in each time slot. 

Make sure to review your preferred course's time slot before registration. Course fees are non-refundable.


8:00 am - 10:00 amPDC AM1: Introduction to Fan-Out Wafer Level Packaging (FOWLP) Beth Keser, Director, Intel Corp.PDC AM2: Semiconductors in Automotive - Technology Trends and Reliability -  Pradeep Lall, Auburn University & Vikas Gupta, ASEPDC AM3: Flip Chip Tech - Mark Gerber, ASE US, Inc.
10:00 am - 10:30 amPDC Coffee Break in Foyer
10:30 am - 12:30 amPDC AM4: Chiplet Design and Heterogeneous Integration Packaging - John Lau, Professor, Unimicron Technology Corp.PDC AM5: Wire Bond Process Development and Optimization - Henri Seppanen, Research Scientist, Kulicke & Soffa Industries & Aashish Shah, Principal Engineer and Technical Lead, Kulicke & Soffa IndustriesPDC AM6: Chip Packaging Processes and Materials - Syed Ahmad, Director, City of Jamestown, ND
12:30 pm - 1:00 pmPDC "Box Lunch" for those taking morning & afternoon classes
1:00 pm - 3:00 pmPDC PM1: Fan Out for Advanced Packaging Applications - John Hunt, Senior Advisor & Jan Vardaman, President, TechSearch International, Inc.PDC PM2: System-in-Package (SiP) - System Solutions Through Miniaturization - Mark Gerber, ASE US, Inc.PDC PM3: Fundamentals of Thermal Management - Rita Mohanty, Sr. Scientific Principal, Henkel Corp.
3:00 pm - 3:30 pmPDC Coffee Break in Foyer
3:30 pm - 5:30 pm

PDC PM4: Polymers for Wafer Level Packaging - Jeffrey Gotro, President, InnoCentrix, LLC

PDC PM5: 3D Flip Chip Package Technology and Assembly Processes - Tom Dory, R&D Manager, Fujifilm Electronic MaterialsCANCELLED PDC PM6: Qualification Formalism for Markets Demanding High Quality & Reliability Standards - Shubhada Sahasrabudhe, Principal Engineer, Corporate, Intel Corp. & Shalabh Tandon, Sr. Director Corporate Quality Network, Intel Corp. 
5:30 pm - 7:00 pm

Welcome Reception

Open to all IMAPS 2022 participants

7:00 pm - 8:00 pm

Equity vs. Equality in the Workplace

Chair: Robin Davis, Deca Technologies
CommitteeErica Folk, Northrop Grumman; Beth Keser, Intel; Dan Krueger, Honeywell; Urmi Ray, iNEMI; Nicole Wongk, Honeywell

This will be a one-hour townhall – open discussion and panel format. Join us for open and lively conversation around many important topics for all to consider in today‘s challenging work environment, including the important differences between equity and equality in the workplace.


KT Moore, Cadence Design Systems - VP Corporate Marketing
Shelby Nelson, Mosaic Microsystems – Chief Technical Officer
Urmi Ray, Saras Micro Devices – Chief Technology Officer
Jean Trewhella, GlobalFoundries - Director of PostFab New Product Introduction
Susan Trulli, Raytheon Technologies, RMD Advanced Microelectronics Solutions – Principal Engineering Fellow

Food & Drink Provided


Course Fees and Inclusions

Course Fees: $325 early registration/$425 after September 2, 2022 per course.

Fees include access to the 2-hour course led by reputable industry leaders.
These fees are non-refundable but may be transferred to another registrant prior to the start of the course. No transfers will be accepted once the course has begun. 

How to Register

  1. Click here to get started.
  2. Log into your member account or create a guest* account.
    *Remember! Member, Nonmember, Speaker, Chair, and Student event registrations include a one-year IMAPS membership. Make sure to populate your account thoroughly. Guest accounts will be converted to member accounts within 30 days of your event registration.
  3. Select the IMAPS 2022 event. 
  4. Select your overall conference registration type (Member, Nonmember, Speaker, Chair, Student).
    Only planning to attend a PDC? Select "PDC Only" as your registration type. PDC-only registrants will not have access to additional conference content. 
  5. Choose your course(s) selection in the time slot drop-down boxes. Select up to one course per time slot.
  6. Check out. You will receive a confirmation email detailing your registration. 

If you need to add or change course selection(s) after completing a registration, please contact IMAPS at

Course Descriptions

Beth Keser, Intel Corp.

              Fan-out wafer level packaging (FO-WLP) technologies have been developed across the industry over the past 15 years and have been in high volume manufacturing for over 10 years. FO-WLP has matured enough that it has come to a crossroads where it has the potential to change the electronic packaging industry by eliminating wirebond and bump interconnections, substrates, leadframes, and the traditional flip chip or wirebond chip attach and underfill assembly technologies across multiple applications. This course will cover the advantages of FO-WLP, potential application spaces; package structures available in the industry; materials, equipment and process challenges; and  reliability.

Semiconductors in Automotive - Technology Trends and Reliability

Vikas Gupta, ASE & Pradeep Lall, Auburn University

The modern car has increased semiconductor content and dollar value.  Semiconductors enable the majority of innovations in automotive.

The first part of the PDC will provide a summary of key disruptive trends in automotive electronics in the upcoming years.  The increased emphasis on autonomous driving as well as electrification of vehicles has resulted in enormous changes for semiconductors and packaging.  Following megatrends will be discussed

  1. Autonomous
    1. Introduction of advanced nodes and packages for processors
    2. Sensing technologies
  2. Electrification
    1. Power systems trend
    2. Wide band gap implementation

In the second part of this professional development course, the design, materials, and reliability strategies for automotive electronics will be presented.  Electronics are increasingly being used in automotive platforms for a variety of mission-critical and safety-critical activities, such as guidance, navigation, control, charging, sensing, and operator interaction.  Over the last two decades, automotive platforms have expanded to incorporate hybrid and fully-electric vehicles.  Much of the electronics is located under the car’s hood or in the trunk, where temperatures and vibration levels are far higher than in consumer office applications.  During the vehicle’s use-life, electronics in the automotive underhood may be exposed to sustained high temperatures of 125-150C for extended periods of time.  The automotive electronics council (AEC) has graded electronics for automotive purposes into four categories: grade-0, grade-1, grade-2, and grade-3.  Grade-0 components have the most demanding criteria of the four grade categories, with predicted power temperature cycling ranging from -40C to +150C for 1000 cycles and ambient temperature cycling ranging from -55C to +150C for 2000 cycles.  Furthermore, the grade-0 components are expected to be capable of sustaining high-temperature storage for 1000 hours at 175C.  With the introduction of new packaging architectures, the area of packaging applications has continued to evolve, allowing for powerful computing on mobile automobile platforms.  New materials and integration technologies have also emerged, allowing for tighter integration of electronics sensing and processing into the structural characteristics of the vehicle.  The automobile platform faces a series of constraints particular to the real-time context for enabling sophisticated functionality. 

Flip Chip Tech
Mark Gerber, ASE US, Inc.

This PDC course will provide a historical overview and background on the evolution of flip chip packaging as well as short market perspective on this platform. Mobile, Infrastructure, Automotive, High Reliability, Medical and High-Performance Network and Computing all rely on Flip Chip technology to enable their silicon solutions.  Although the use of new technologies such as Fan-Out hold promise for certain applications, flip chip advancements continue to challenge many new technology competitors from a price and reliability perspective and may end up driving hybrid approaches.  Interconnect structure, process flows, materials and package integration process methods for evolving Flip Chip applications will be discussed in detail. Understanding the trade-offs between the different bump structures and package platforms is key in determining the silicon device layout and the type of design rules that can be leveraged for new products. As part of this course, the assembly process details will be discussed and will include Mass Reflow, Thermo-Compression Non-Conductive Paste (TCNCP) bonding and Laser Assisted Bonding. Reliability aspects such as IMC formations and ways to address will also be covered as a key consideration for Interconnect decisions.

Chiplet Design and Heterogeneous Integration Packaging
John Lau, Professor, Unimicron Technology Corp. 

Chiplet is a chip design method and heterogeneous integration (HI) is a chip packaging method. HI uses packaging technology to integrate dissimilar chips, photonic devices, and/or components (either side-by-side, stacked, or both) with different sizes and functions, and from different fabless design houses, foundries, wafer sizes, feature sizes and companies into a system or subsystem on a common package substrate. These chips can be any kind of devices and don't have to be chiplets. On the other hand, for chiplets, they have to use the heterogeneous integration to package them. For the next few years, we will see more implementations of a higher level of chiplet designs and HI packaging, whether it is for time-to-market, performance, form factor, power consumption or cost. In this lecture, the introduction, recent advances, and trends in chiplet design and HI packaging will be presented. 
Course Outline: 
1. Introduction 
2. System-on-Chip (SoC) 
3. Chiplet Design and HI Packaging 
4. Advantages and Disadvantages of Chiplet Design and HI Packaging 
5. AMD Chiplet Design and HI Packaging: (a) EPYZ and (b) RYZEN 
6. Intel Chiplet Design and HI Packaging: (a) FOVEROS, (b) FOVEROS Direct, and (c) Ponte Vecchio 
7. TSMC chiplet Design and HI Packaging: (a) SoIC, (b) SoIC + CoWoS, and (c) SoIC + InFO PoP 
8. Chiplets Lateral Interconnects (Bridges): (a) Intel's EMIB, (b) IBM's solution for EMIB, (c) Applied Materials' Bridge Embedded in Fan-Out EMC, (d) SPIL's FO-EB, (e) TSMC's LSI, (f) ASE's sFOCoS, (g) IME's EFI, and (h) Amkor's S-Connect Fan-Out Interposer 
9. HI Packaging on Organic Substrates: many examples 
10. HI Packaging on Silicon Substrates (TSV-Interposers): many examples: (a) Leti, (b) IME, (c) HKUST, (d) ITRI, (e) Xilinx/TSMC, (f) Altera/TSMC, (g) NVidia/TSMC, (h) AMD/UMC, (i) AMD's Active Interposer, (j) Intel's FOVEROS, (k) TSMC's SoIC, and (l) Samsung's X-Cube 
11. HI Packaging on Silicon Substrates (TSV-Less Interposers) such as Bridges: Same as 8 
12. HI Packaging on Ceramic Substrate: one example 
13. HI Packaging on Fan-Out RDL for High Performance Applications: many examples: (a) STATSChipPac's FOFC-eWLB, (b) ASE's FOCoS, (c) MediaTek's FO-RDLs, (d) TSMC's InFO_oS and InFO_MS, (e) Samsung's Si-Less RDL Interposer, (f) TSMC's RDL-Interposer, (g) ASE's FOCoS (Chip-Last), (h) Shinko's Organic RDL-Interposer, and (i) Unimicron's Hybrid Substrate 
14. Assembly Technologies for Chiplet Design and HI Packaging: (a) SMT, (b) Solder Bumped Flip Chip, (c) CoW, (d) WoW, (e) TCB, and (f) Bumpless Cu-Cu Hybrid Bonding 
15. Trends in Chiplet Design and HI Packaging

Wire Bond Process Development and Optimization
Henri Seppanen, Research Scientist, Kulicke & Soffa Industries; & Aashish Shah, Principal Engineer and Technical Lead, Kulicke & Soffa Industries

This wire bonding professional development course provides deep dive into wire bonding technologies, techniques, process development, and optimization. The course will introduce wire bonding technologies from thin wire ball bonding and large wire wedge bonding to heavy ultrasonic copper ribbon bonding. After the introduction we present wire bonding fundamentals, the physics of bonding, and material science to understand the bonding process, process optimization, and reliability. We share practical methods for the wire bond process optimization, including parameter selection, destructive and non-destructive testing, and how to use analysis tools such as trace analysis, DOE, and response surface. This course is for anyone who wants to learn or deepen their understanding of wire bonding. Beginners will get practical information on how to improve the bonding process and seasoned professionals will get in-depth science-based knowledge in wire bonding, including references and links to the source materials.

Chip Packaging Processes and Materials
Syed Ahmad, Director, City of Jamestown, ND

Advanced Chip Packaging The course presents manufacturing, materials, quality and reliability info in terms understandable to engineering and non-engineering personnel. Packaging characteristics and drivers will be outlined. Types of packages and critical differences among them and their applications will be discussed. The course will look at the design selection to meet use and application environments. Step-by step manufacturing 
flow for plastic packages will be presented as an example to understand the complexity of processes, materials and equipment involved in their manufacture. Advanced packaging will be introduced. Materials selection with respect to application environments will be discussed. Quality and reliability issues related to chip packaging and assembly and their solution will be outlined.

Fan Out for Advanced Packaging Applications
John Hunt, Senior Advisor & Jan Vardaman, President, Techsearch International, Inc.

Fan Out technology has evolved as an alternative package to meet both the need for miniaturization of electronics, and for the complex interconnectivity of advanced packages such as recent chiplet applications.   
The wide use of mobile and IOT devices coming into more common use has driven the need for increased capability of data centers.  Fan Out technology is now in production for many of these applications.  It has enabled the heterogeneous integration of die and memory with improved electrical performance and lower cost than traditional 2.5 packaging for these data center requirements. 
We will review how the integration of wafer level processing technologies; substrate evolution and Flip Chip packaging structures have come together with recent advances in both low density and high-density Fan Out packaging.  These packages are for automotive, IoT, advanced mobile, server and AI applications.  They can have higher levels of integration and sophistication than has ever been possible in the past with traditional packaging techniques.  A brief overview of the concept of Fan Out packaging, the  history of its evolution, and recent Fan Out developments to meet a variety of applications including the integration of chiplets into advanced packages will be discussed in this course.

System-in-Package (SiP) - System Solutions Through Miniaturization
Mark Gerber, ASE US, Inc.

This PDC course will introduce the package platform SiP (System-in-Package) and how some companies are diversifying from SOC (System-on-a-Chip) to leverage heterogeneous silicon integration and package miniaturization to enable system level solutions. A short market perspective will be reviewed as well as how industry segments are leveraging SiP and how the OEM market is evolving and creating system level ecosystems to enabling content revenue- a key area of IOT. SiP general process flow details will be covered as well as key process considerations for yield improvements. In addition, a brief overview of some of the tools that may be leveraged to help miniaturize module solutions and improve performance. This class will also introduce several variations of the SIP platform using Fan-Out Wafer Level packaging and new embedded substrate technologies are also emerging as powerful future platforms to enable lower power and higher performance devices using solderless interconnects.

Fundamentals of Thermal Management
Rita Mohanty, Sr. Scientific Principal, Henkle Corp.

The cooling of electronics is critical to the safety, performance and reliability of any device or system. Microelectronic devices for space, 5G, power electronics, automotive and IOT applications can generate a large amount of heat. If not managed properly, this heat can have catastrophic impact on the device and system. Design engineers must consider appropriate thermal management approach to meet today's stringent requirements for device reliability. This course is designed to give the engineers an overview of fundamentals of passive thermal management using Thermal Interface Materials (TIM) followed by practical guideline in choosing the right thermal solution for your application.

Polymers for Wafer Level Packaging
Jeffrey Gotro, President, InnoCentrix, LLC

The course has been completely updated to include a detailed discussion of the polymers and polymer-related processing for Fan-Out Wafer Level (FOWLP) packaging as well as Fan-Out Panel Level packaging (FOPLP). The course will provide an overview of the important structure-property-process-performance relationships for polymers used in wafer level packaging.  The main learning objectives will be: 

1) Gain insights on how polymers are used in Fan Out Packaging, specifically mold compounds and polymer redistribution layers (RDL) 
2) Understand the key polymer and processes challenges in Fan Out Wafer Level Packaging 
3) Learn about polymers and processes used in Fan Out Panel Level Packaging including new materials for mold compounds and a detailed description of the polymers used for RDL in FOPLP. 

Course Topics:
Overview of polymers used in Wafer Level Packaging, Wafer level process flows (chip first versus chip last (RDL first)) Epoxy Mold compounds for eWLP,  Photosensitive polyimides and polybenzoxazoles, Polymer reliability challenges in Fan-out wafer level packaging, Processes and materials for Fan Out Panel Level Packaging, Wafer versus panel processing; polymer challenges and solutions

Packaging engineers involved in the development, production, and reliability testing of semiconductor packages would benefit from the course. R&D professionals interested in gaining a basic understanding of the structure/property/process/performance relationships in polymers and polymer-based materials used in electronic packaging will also find this course valuable.

3D Flip Chip Package Technology and Assembly Processes
Tom Dory, R&D Manager, Fujifilm Electronic Materials

This PDC will provide an improved understanding of new flip chip package options and assembly flows. Flip chip packaging assembly is not new. But newer package requirements require more connections die to die and die to package, a tighter bump pitch and more functionally in the package. Laptop computers, tablets and smart phones, using flip chip packaging with thinned die and package substrates are driving new assembly requirements.  New technology drivers bring new assembly challenges that will be discussed in this PDC. This PDC begins with a discussion of current flip chip assembly including 2.5 (interposer) & 3D package assembly. We will discuss the newer 3D technology options and challenges. These assembly challenges include copper pillar bonding, bump stack material changes, tighter bump pitch, underfill flow and no-flow options, new under fill materials, thermal management with improved thermal interface materials (TIM), embedded passives, and die attach films. Current wafer thinning process options dicing and handling thin wafers and die will be covered. Newer bump materials will be discussed with their impact to flip chip or stacked die package assembly.

Qualification Formalism for Markets Demanding High Quality & Reliability Standards
Shubhada Sahasrabudhe, Principal Engineer, Corporate, Intel Corp.
& Shalabh Tandon, Sr. Director Corporate Quality Network, Intel Corp.

Recent times have accelerated the digitization of world infrastructure (online shopping, medical services, enterprise operations, workforce displacement are a few examples) driving tremendous growth in the high-performance computing industry. The commoditization of semiconductor devices has enabled growth in artificial intelligence enabling new markets such as IOT, industrial automation, automotive and edge devices predicting >50B connected ’things‘ in this decade. To enhance device functionality, connectivity and performance, packaging is also undergoing a transformation. Innovations in 2.5D, 3D package architectures are enabling heterogeneous integration of various IPs on mixed silicon to deliver better computational experience in shorter time to market while managing cost. For new emerging markets such as ADAS1, product quality, reliability and availability are paramount for secure operation of vehicles. Similarly, edge computing is driving high performance and long life for base station products. These markets require a different approach to product and technology qualification than the legacy products in PCs. It is imperative we assess quality and reliability of such diverse products by understanding the relevant boundary conditions and characterizing their responses to a variety of mission profiles they will be exposed to. This course will present a qualification formalism that takes an integrated approach of understanding the physics that drives semiconductor failure mechanisms and combines with the mission profiles and use conditions (UC) of the new markets to enable product qualifications. Authors will focus on automotive and edge market driven product needs as examples to elaborate on quality and reliability assessment methodology.
This course is structured in three sections. Section 1 discusses fundamentals of quality and reliability and will introduce key elements such as UC, accelerated life tests, statistical data analysis methods, acceleration factor models, failure risk assessment, design for reliability and design of experiments. Section 2 discusses the physics-based reliability assessment methodology where mechanistic understanding along with failure reliability statistics are used effectively to develop predictive models for proactive risk assessments and influencing technology decisions. Section 3 will combine the formalism described in the first 2 sections to highlight qualification challenges and solutions for the automotive and edge space. The authors will use examples of either package or silicon failure mechanisms, characterization methodologies used to assess risks and risk mitigation approaches to solving the problem. The benefits of use condition and physics-based reliability assessment methodology will be emphasized through case studies across multiple packaging key challenges like solder joint reliability, package warpage impact to surface mounting, die cracking and Si-Pkg interactions. Multiple hands-on exercises are designed throughout the course to reinforce the concepts discussed and enable practical learning.

Course outline:
• Packaging technology trends & challenges
• Introduction to quality & reliability
• Overview of key components of reliability statistics and accelerated testing
• Hands-on Class Exercise - I
• Introduction to physics-based reliability modeling
• Key components of modeling: Stress/Strain curves, Failure Theories, Finite Element Analysis, material degradation, etc.
• Reliability Model development and Analysis Validation Techniques
• Key failure mechanisms
• Application of methodology to automotive and edge space
• Hands-on Class Exercise - II
• Summary of key learning elements