Virtual Live On-Line Workshop

The  Heterogeneous Integration Roadmap (HIR) is a roadmap to the future of electronics identifying technology requirements and potential solutions. The primary objective is to stimulate pre-competitive collaboration between industry, academia and government to accelerate progress. The roadmap offers professionals, industry, academia and research institutes a comprehensive, strategic forecast of technology over the next 15 years. The HIR also delivers a 25-year projection for heterogeneous integration of Emerging Research Devices and Emerging Research Materials with longer research-and-development timelines. The HIR is sponsored by three IEEE Societies (Electronics Packaging Society, Electron Devices Societry & Photonics Society) together with SEMI and ASME Eeelctronics & Photonics Packaging Division.  

This HIR workshop @ IMAPS SiP Confeence  will start with a guest keynote to highlight future challenges from automotive electronics industry perspective. We shall then feature seven selected topics from the HIR chapters including an overview presentation.  The purposes for the HIR workshop at IMAPS SIP Confereence are to feature technology innovation & advancements & stimulate collaboration around the world.

Organizing Committee: Chair: William Chen, Co-Chairs, WR Bottoms, Vikas Gupta  

Agenda

KEYNOTE: 5G Paves the New Phase of the Packaging Technology

Choon Lee, JCET Group

   5G is going to allow most high bandwidth users to access their mobile radio communication more efficiently. It can be possible through new or enhanced packaging technologies that include denser form factor-oriented and antenna embedded/separated structures. This talk will share the 5G related packaging technologies which enable 5G mobile products to be accommodated within allowed board space. 

KEYNOTE: On the Development of mmW Surface Mount Antenna for Automotive SIP Wireless Products at the Network Edge

Joy Laskar, MAJA Systems

   There has been growing interest in adoption of millimeter- wave technology for high-speed data transport to compliment current enterprise technologies, such as optical and metal-based interconnects, offering substantial advantages in band-width, reach, power consumption, and cost. It has been only recently, with the emergence of mmW radio ICs in combination with innovative antenna technology that one can envision a new class of systems and applications for low delay and high throughput connectivity. In this presentation, we focus on recent breakthroughs in Surface Mount Antenna technology enabling wireless SIP products for automotive customers at the edge of the network providing solutions for wireless data ingestion, improved connectivity and signal integrity.

Panel Session: SiP Challenges for 5G

The 5G rollout is underway for both sub 6GHz and mmWave.  The design, fabrication, and test of SiPs, especially to support mmWave 5G applications, present challenges.  This panel will discuss issues including design, materials, and test. 

Panelists; Michael Liu, Director, JCET Group; Nozad Karim, Amkor Technology; Mark Gerber, ASE; Tanja Braun, Fraunhofer; David Vye, Cadence

Moderator: Jan Vardaman, TechSearch International

KEYNOTE: From 5G mmWave to 6G THz: What’s Next in RF Test Challenges?

Jeorge Hurtarte, Teradyne

   As each G in mobile networks generations takes about eight years to follow the previous one, we’re only about five years from facing new 6G THz test challenges.    And given that 5G mobile networks are just ramping up with high volume millimeter wave devices, is it too early to start worrying about 6G test challenges?   This presentation starts with an overview of the possible 6G use cases that make THz a requirement as we enter into the second half of this decade and then follows with a preview of the test challenges that can be expected for 6G beyond the current 5G millimeter wave test challenges.

KEYNOTE: optical I/O Chiplets for Next-Generation Heterogeneous Computing

Mark Wade, Ayar Labs

Electrical communications technologies are facing challenges in scaling bandwidth while achieving compelling energy efficiency, bandwidth density, latency, and reach. While digital processing performance continues to scale in how much compute can be achieved per unit area of silicon, the ability to fuel processing cores with bandwidth has become a major limiting factor for many high-value workloads, such as machine learning. A new I/O technology is needed that can match the performance requirements needed for computing fabrics and have a viable path to scale to high-volumes. In this talk, we present progress towards a new generation of densely integrated optical I/O technologies that address the bandwidth density, energy efficiency, and scalability requirements for next-generation computing fabrics and demonstrate a new overall chip-to-chip I/O architecture based on this technology.

Panel Session on:
Chiplet Integration for HPC Applications - Enabling Mass Adoption

The industry shift to hetero/homogeneously integrated based chip design solutions has started and initial products have been introduced by several leading player who have the ability to vertically control the device and interface designs for all parts of the integrated solution.  The topic we want to address is what are the challenges and opportunities that will enable broad based adoption of this new paradigm in the design of advanced server and network processors and SoC’.

Panelists: Jeorge Hurtarte, Teradyne; Ravi Agarwal, Facebook; Kevin Quillen, ANSYS;
Amit Marathe, Google

Moderator: Eelco Bergman, ASE Group

HPC/Chiplet Integration

SiP Test & Yield Enablement

Packaging Challenges and Opportunities for mmWave Communications
Dr. Madhavan Swaminathan, Georgia Tech

Ravi Agarwal, Facebook

Chris Scanlan, Besi

SiP Test Solution for 5G/IoT
Vineet Pancholi, Amkor Technology

Minimizing deleterious radiation effects in sensitive CMOS devices while maintaining 100% coverage strategies for X-ray defect inspection in double-sided SiP manufacturing
Francisco Machuca, SVXR

Overview of Warpage and Void Simulations for System in Package (SiP)
Eric Ouyang, JCET