SiP Agenda
The top global virtual event for Advanced System-in-Package technologies!
Combining the 3D ASIP and IMAPS SiP events into an exciting, comprehensive program:
One event covering SiP technology developments, solutions and business trends.
Monday, June 20th | 9:00am-12:30pm
Heterogeneous Integration Roadmap (HIR) Workshop
HIR Agenda:
HIR Session Introduction: Mark Gerber, SiP General Chair and Bill Chen HIR Introduction
Bill Chen, ASE
Vikas Gupta, ASE
Mehdi Asheghi, Stanford University
Bill Chen, ASE
12:15 pm - 1:00 pm -- HIR WORKSHOP LUNCH
PDC Courses
Tom Dory, Fujifilm Electronic Materials USA
Mark Gerber, ASE US, Inc.
Break
PDC3: Chiplet Design and Heterogeneous Integration Packaging
John H. Lau, Unimicron Technology Corporation
Tuesday, June 21st
7:00am - 8:00am | Breakfast | |
8:00am - 8:15am | Opening Remarks: Mark Gerber, ASE US, Inc. | |
8:15am - 9:00am | KEYNOTE: System-level Optimization Opportunities and Challenges in the Era of Slowing Silicon Process Technology Silicon process technology-based shrink, which has been slowing in the recent years, has led to growth in die size of most chipsets, including mobile. Splitting the die has become a mandatory practice and compute platforms, that are usually at larger sizes, have been leading the way. Mobile must follow suit. A system perspective, and sound architectural understanding, are essential to delivering the power and performance on these split die heterogeneous systems. Some of the challenges and opportunities of these heterogeneous integrations will be reviewed.
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9:00am - 9:45am | KEYNOTE: Silicon SiPs for the Metaverse One of the enduring societal lessons of the past two years revolves around the fragility – and the deep importance – of personal and social engagement. At Meta’s Reality Labs we build tools that connect people and bridge distance, and we see that mission as increasingly relevant to tomorrow. The technical challenges in enabling AR and VR are immense, and many of the focus on the ecosystem around customized silicon. But with challenges come opportunities for innovation, and in this talk I will discuss some of our ideas. | |
9:45am - 10:30am | Break in Exhibit Area | |
Exhibit Tables open 9:45am - 6:30 pm | ||
Session 1: 5G/Mobile Chair: Steven Kummerl, Texas Instruments | ||
10:30am -11:00am | Warpage Simulation and Measurement of a SIP Module for Laptop CPU Applications | |
11:00am - 11:30am | Next generation RF Front End Based SiPs: Platform Needs, Features and Design Considerations | |
11:30am - 12:00pm | Multi-terminal thin Silicon Capacitors enabling best in-package decoupling strategy for Mobile and HPC Mohamed Jatlaoui, Murata | |
12:00pm - 1:30pm | Lunch & Networking with Exhibitors Thank you to our sponsor: | |
Session 2: Wearables/IoT Chair: Bob Patti, Nhanced | ||
1:30pm - 2:00pm | Empowering Front-End Cellular Innovations with Advanced SiP Solutions Curtis Zwenger, Amkor Technology | |
2:00pm - 2:30pm | Flexing, Bending and Stretching to the Future of Wearable Medical Devices | |
2:30pm - 3:00pm | Innovative Materials for Advanced Packaging and System in Package (SiP) Szi Pei LIm, Indium Corp. (Dongkai Shangguan) | |
3:00pm - 4:00pm | Break - in Exhibitor Area Thank you to our sponsor: | |
4:00pm - 5:30pm | Tuesday Panel Session on Moderator: Jan Vardaman, TechSearch International The rollout of 5G is underway. A variety of substrate materials are used in 5G mmWave applications, including LTCC, flex circuit, and low-loss laminate substrates such as BT resin, FR-4, and build-up film. Polymer redistribution materials are used for WLP and glass is also an option. Liquid crystal polymer is used for the antenna in some applications. Will any one material dominate the package? Will packages use antenna-in-package (AiP) or is antenna on chip (AoC) more common? Are there test issues with the different antenna designs? The panel will address these questions. Panelists: Mark Gerber, ASE US Matthew Poulton, Qorvo Additional panelists soon | |
5:30pm - 6:30pm | Exhibit Reception Thank you to our sponsors: | |
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7:00am - 8:00am | Breakfast | ||||||||
8:00am - 8:15am | Opening Remarks: Steven Kummerl, Texas Instruments | ||||||||
8:00am - 8:45am | KEYNOTE: Trends and Reliability Challenges in Advanced Driving Assistance System (ADAS) Fast changing in autonomous driving applications make the whole automotive industry becoming a transformation process. The car has become a product that integrates all possible variants of complex semiconductor-based functions from both HW and SW, including AI. The automotive industry now requires IC with high performance, low power, and made from resilience capable (fail operational) robust technologies. This likely introduces complexed pictures in aspects of HW/SW maintenance, safety, security, reliability, and cost. New challenges, thus, take places due to evolving complexity of IC construction and connection technologies. As a result, the impacts of additional challenges on reliability are enormous and need to be addressed. However, these challenges also provide opportunities for innovative thinking. | ||||||||
8:45am - 9:30am | KEYNOTE: Automotive Packaging Ecosystem Anindya Poddar, Texas Instruments | ||||||||
9:30am - 10:15am | Break in Exhibits Area | ||||||||
Exhibit Tables open 9:30am - 3:30 pm | |||||||||
Session 3: HPC/SiP Chair: Eelco Bergman, ASE Group | |||||||||
10:15am - 10:45am | The Path to a Sub fJ/bit Interconnect Daniel Graf, Zero EC | ||||||||
10:45am - 11:15am | Advanced Fanout Embedded Bridge Packaging Technology for Chiplets Integration Lihong Cao, ASE Group | ||||||||
11:15am - 11:45am | Hybrid Bonding - A Key to the Future Robert Patti, Nhanced Semi. | ||||||||
11:45am - 1:15pm | Lunch & Networking with Exhibitors Thank you to our sponsor: | ||||||||
Session 4: Automotive & Power | |||||||||
1:15pm - 1:45pm | Packaging Technology for Automotive Power Delivery | ||||||||
1:45pm - 2:15pm | Assurance of Sustained High Temperature Reliability for Underfills and Interfaces in FCBGAs for Automotive Underhood Operation | ||||||||
2:15pm - 2:45pm | Packaging Technology for Beyond 100kW/L Mike Marczi, Marel Power | ||||||||
2:45pm - 3:30pm | Break - In Exhibitor Area | ||||||||
Exhibits close following Break | |||||||||
3:30pm - 5:00pm | START-UP COMPETITION Thank you to our sponsor: Start-up Companies: The start-up competition session will feature brief presentations by each of the four start-up companies listed above, which will be evaluated by a panel of selected judges and a winning company will be selected during this live session. | ||||||||
5:00pm - 6:30pm | Panel Session on Moderator: Eelco Bergman, ASE Group As the semiconductor industry continues to advance its roadmap, we have started seeing a marked shift to chiplet based, heterogeneously integrated, silicon system architectures for a variety of reasons including performance, cost and yield optimization. The initial implementations have been primarily by the leading semiconductor manufacturers and wafer foundries. The advantages for cost/yield optimization, bandwidth, performance, latency, mixed technology integration, etc. are evident, so this panel will explore what’s going to be required for the industry to adopt this new design paradigm on a much broader scale.
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6:30pm - 8:00pm | Sip at SiP Thank you to our sponsor:
Ticketed event only - select number of wine tickets as an add-on to your conference registration - $50 per person Purchase wine tickets - select # of wine tickets on page 2
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Thursday, June 23rd
7:00am - 8:00am | Breakfast |
8:15am - 9:00am | KEYNOTE: Conducting the Semiconductors: The Role of Design in the SysMoore Era As manufacturing technology around advanced packaging evolves, the performance and density of designs being enabled have experienced tremendous advancement in the past decade. The next decade is the time for the EDA industry to give wings to chip and system designers of the SysMoore era. In this talk, we will introduce the roles of design elements such as die-to-die interface IP, end-to-end EDA automation, and test / debug / life cycle management play in advanced packaging. We will also discuss some future challenges in complexity of design, verification, and security. |
Session 5: EDA/Design Chair: Curtis Zwenger, Amkor Technology | |
9:00am - 9:30am | Design and Analysis Challenges for Multi-chiplet 3D Integration John Park, Cadence |
9:30am - 10:00am | Enabling a Chiplet based Ecosystem Anthony Mastroianni, Siemens |
10:00am - 10:45am | Break |
Session 6: Test / Inspection Chair: Habib Hichri, Ajinomoto | |
10:45am - 11:15am | Test Impact of Chiplets in Packages Warren Wartell, Amkor Technology |
11:15am - 11:45am | 5G RF Front End System in Package(SiP) Test ChallengesD Wei Wang, NI |
11:45am - 12:15pm | What‘s the Future of Final Test? |
12:15pm | Closing Remarks |