The top global virtual event for Advanced System-in-Package technologies!
Combining the 3D ASIP and IMAPS SiP events into an exciting, comprehensive program:
One event covering SiP technology developments, solutions and business trends.
Monday, August 9th
Heterogeneous Integration Roadmap (HIR) Workshop
HIR Workshop - Bill Bottoms and Bill Chen, ASE Group
The Heterogeneous Integration Roadmap (HIR) is a roadmap to the future of electronics identifying technology requirements and potential solutions. The primary objective is to stimulate pre-competitive collaboration between industry, academia and government to accelerate progress. The roadmap offers professionals, industry, academia and research institutes a comprehensive, strategic forecast of technology over the next 15 years. The HIR also delivers a 25-year projection for heterogeneous integration of Emerging Research Devices and Emerging Research Materials with longer research-and-development timelines. The HIR is sponsored by three IEEE Societies (Electronics Packaging Society, Electron Devices Societry & Photonics Society) together with SEMI and ASME Eeelctronics & Photonics Packaging Division.
This HIR workshop @ IMAPS SiP Confeence will start with a guest keynote to highlight future challenges from automotive electronics industry perspective. We shall then feature seven selected topics from the HIR chapters including an overview presentation. The purposes for the HIR workshop at IMAPS SIP Confereence are to feature technology innovation & advancements & stimulate collaboration around the world.
- Invited Keynote : System Integration and Reliability – A Vision for Automotive Packaging: Thorsten Meyer (Infineon)
- HIR Overview: William Chen & WR Bottoms (3MTS)
- Automotive Electronics: Rich Rice (ASE), Veer Dhandapani (NXP)
- SiP & Module: R. Aschenbrenner (IZM) , Klaus Pressel (Infineon), Erik Jung (IZM)
- MEMS & Sensor Integration: Shafi Saiyed (Analog Devices) & MaryAnn Mahar (Soft MEMS)
- Integrated Power Electronics: Patrick McCluskey (U Md) & Douglas Hopkins (NCSU)
- Modelling & Simulation: Christopher Bailey (Greenwich U) & Xuejun Fan (Lamar U)
- Reliability: Abjijit Desgupta (U Md), Richard Rao (Inphi), Shubhana Sahasrabudhe (Intel)
- Workshop Q&A and Wrap-Up: William Chen & Bill Bottoms
PDC: System-in-Package (SiP) - System Solutions Through Miniaturization - Mark Gerber, ASE US
This PDC course will introduce the package platform SiP (System-in-Package) and how some companies are diversifying from SOC (System-on-a-Chip) to leverage heterogeneous silicon integration and package miniaturization to enable system level solutions. A short market perspective will be reviewed as well as how industry segments are leveraging SiP and how the OEM market is evolving and creating system level ecosystems to enabling content revenue- a key area of IOT. SiP general process flow details will be covered as well as key process considerations for yield improvements. In addition, a brief overview of some of the tools that may be leveraged to help miniaturize module solutions and improve performance. This class will also introduce several variations of the SIP platform using Fan-Out Wafer Level packaging and new embedded substrate technologies are also emerging as powerful future platforms to enable lower power and higher performance devices using solderless interconnects.
PDC: 3D Packaging Assembly and Technology for Mobile Devices - Tom Dory, Fujifilm
This PDC provides details on current and future assembly 3D packaging processes and technologies. The 3D IC and wafer-level packaging area is forecasted to grow to over $170 billion by 2022 driven by mobile devices including phone, tablet and laptop computers and gaming devices. Advanced packaging requirements require the evolution of back end manufacturing to become more process control driven. The 3D stacked die TSV packaging has advantages, but only in some market segments. In the cell phone market, stacking chips helps to minimize some of the interconnect issues between the logic and the memory chips. Wire bonding remains a key assembly method for 3D memory packages with a separate assembly process flow.
This PDC will cover 3D and 2.5D (interposer) designs, 3D assembly flow, known good die, KGD, concerns, 3D package testing issues, supply line logistics, thermal management, logic bump out designs, wafer thinning and handling (thermal & laser debonding and residue removal) and interposers with microfluidics cooling built-in. The objective of this PDC is to provide the students with an overview of the technologies, materials, and processes involved in the latest 3D and 2.5D assembly processes.
Tuesday, August 10th
SiP Solutions for 5G/IOT
SiP Solutions for Automotive, Industrial & Power
KEYNOTE: 5G Paves the New Phase of the Packaging Technology
Choon Lee, JCET Group
5G is going to allow most high bandwidth users to access their mobile radio communication more efficiently. It can be possible through new or enhanced packaging technologies that include denser form factor-oriented and antenna embedded/separated structures. This talk will share the 5G related packaging technologies which enable 5G mobile products to be accommodated within allowed board space.
KEYNOTE: On the Development of mmW Surface Mount Antenna for Automotive SIP Wireless Products at the Network Edge
Joy Laskar, MAJA Systems
There has been growing interest in adoption of millimeter- wave technology for high-speed data transport to compliment current enterprise technologies, such as optical and metal-based interconnects, offering substantial advantages in band-width, reach, power consumption, and cost. It has been only recently, with the emergence of mmW radio ICs in combination with innovative antenna technology that one can envision a new class of systems and applications for low delay and high throughput connectivity. In this presentation, we focus on recent breakthroughs in Surface Mount Antenna technology enabling wireless SIP products for automotive customers at the edge of the network providing solutions for wireless data ingestion, improved connectivity and signal integrity.
Panel Session: SiP Challenges for 5G
The 5G rollout is underway for both sub 6GHz and mmWave. The design, fabrication, and test of SiPs, especially to support mmWave 5G applications, present challenges. This panel will discuss issues including design, materials, and test.
Panelists; Michael Liu, Director, JCET Group; Nozad Karim, Amkor Technology; Mark Gerber, ASE; Tanja Braun, Fraunhofer; David Vye, Cadence
Moderator: Jan Vardaman, TechSearch International
PDC: 5G mmWave package development requirements and solutions- Urmi Ray, Consultant
The fifth Generation (5G) mobile communication era is expected to address the insatiable need for data communication by introducing mmWave technology and protocols. The unprecedented latencies offered by 5G Networks will enable users to indulge in gigabit speed immersive services regardless of geographical and time dependent factors.
The key to enabling this architecture is packaging and system integration, especially involving an effective antenna structure and RFIC communication in cost-effective, small form-factor packages. As full speed development, demonstration and qualification of mmWave systems have accelerated in 2017, different design and packaging architectures are emerging.
This PDC will provide a comprehensive landscape of package development options including LTCC, eWLB/FOWLP as well as laminate based packaging. The specific requirements of materials and process needs (low dielectric material, copper roughness requirements) are discussed. Multiple different package structures are presented as case studies to demonstrate comparative performance of eWLB vs laminate packages. Product application spaces ranging from mobile/handheld to network infrastructures and automotive/satellite radars are highlighted. Key aspects and guidelines towards a cost/performance trade-off analysis will be summarized.
PDC: Substrate for Heterogeneous Integrations (SiPs) - John Lau, Unimicron Technology Corporation
Heterogeneous integration or SiP (system-in-package) uses packaging technology to integrate dissimilar chips, photonic devices, and/or components (side-by-side and/or stack) with different materials and functions, and from different fabless design houses, foundries, wafer sizes, feature sizes and companies into a system or subsystem. For the next few years, we will see more implementations of a higher level of heterogeneous integration, whether it is for time-to-market, performance, form factor, power consumption or cost. In this lecture, the introduction, recent advances, and trends in chiplets and heterogeneous integrations will be presented. The lecture materials are mainly from the papers from others and the latest books (Heterogeneous Integrations 2019 and Semiconductor Advanced Packaging 2021) authored by the lecturer and every attendee will receive more than 120 pages of lecture handouts.
SiP Solutions for 5G/IOT
SiP Solutions for Automotive, Industrial & Power
KEYNOTE: Ever Smaller: The Increasing Viability of SiPs in Consumer Electronics
Pieris Berreitter, Fitbit/Google
The wrist of the average human has changed very little over the course of human history; meanwhile, our expectation of what's possible in a watch seems to have no bounds. As this appetite for features increases we are compelled as product developers to focus our miniaturization lens beyond the obvious targets. This talk will cover some classical SiP solutions as well as some less obvious candidates, addressing challenges unique to the consumer electronics industry. While the examples we will cover in this talk are derived from smartwatches, the fundamental elements apply to all space-constrained designs.
KEYNOTE: Chiplets and Heterogeneous Integration Bring a New Twist to SiP
Keith Felton, Siemens EDA
The semiconductor industry is facing an inflection point as higher cost, lower yield, and reticle size limitations drive the need for viable alternatives to traditional monolithic solutions, which have hit the limits of physics. This is driving an emerging trend to disaggregate what typically would be implemented as an SoC into solid, fabricated IP blocks, otherwise known as chiplets. These chiplets typically include just a couple of functions implementated at the optimal process node, when combined with other chiplets, memory and often a custom ASIC results in a multi-die heterogeneous integrated implementation that typically utilizes a high-performance substrate ushering in a new generation of system-in-package and with it a new set of design challenges that we will explore.
Moderator: Urmi Ray, Consultant
SiP market and technology trends for wearables applications
Santosh Kumar, Yole
Bio-sensing and its Integration in Wearables
Henry Lin, ASE Group
Dave McCann, Rockley Photonics
Strategies for 2.xD and 3D Integration
Javi DeLaCruz, ARM
Design Flow Challenges for Silicon-centric
John Park, Cadence
Ansys: Solving the Unsolvable
Kevin Quillen, ANSYS
Thursday, August 12th
HPC/SiPh, Chiplet Integration
SiP Test & Yield Enablement
KEYNOTE: From 5G mmWave to 6G THz: What‘s Next in RF Test Challenges?
Jeorge Hurtarte, Teradyne
As each G in mobile networks generations takes about eight years to follow the previous one, we‘re only about five years from facing new 6G THz test challenges. And given that 5G mobile networks are just ramping up with high volume millimeter wave devices, is it too early to start worrying about 6G test challenges? This presentation starts with an overview of the possible 6G use cases that make THz a requirement as we enter into the second half of this decade and then follows with a preview of the test challenges that can be expected for 6G beyond the current 5G millimeter wave test challenges.
KEYNOTE: optical I/O Chiplets for Next-Generation Heterogeneous Computing
Mark Wade, Ayar Labs
Electrical communications technologies are facing challenges in scaling bandwidth while achieving compelling energy efficiency, bandwidth density, latency, and reach. While digital processing performance continues to scale in how much compute can be achieved per unit area of silicon, the ability to fuel processing cores with bandwidth has become a major limiting factor for many high-value workloads, such as machine learning. A new I/O technology is needed that can match the performance requirements needed for computing fabrics and have a viable path to scale to high-volumes. In this talk, we present progress towards a new generation of densely integrated optical I/O technologies that address the bandwidth density, energy efficiency, and scalability requirements for next-generation computing fabrics and demonstrate a new overall chip-to-chip I/O architecture based on this technology.
Panel Session on Heterogeneous Integration
Moderator: Eelco Bergman, ASE Group
SiP Test & Yield Enablement
Packaging Challenges and Opportunities for mmWave Communications
Dr. Madhavan Swaminathan, Georgia Tech
Ravi Agarwal, Facebook
SiP Test Solution for 5G/IoT
Vineet Pancholi, Amkor Technology
Minimizing deleterious radiation effects in sensitive CMOS devices while maintaining 100% coverage strategies for X-ray defect inspection in double-sided SiP manufacturing
Francisco Machuca, SVXR
Overview of Warpage and Void Simulations for System in Package (SiP)
Eric Ouyang, JCET