8:15am - 9:00am

KEYNOTE: System-level Optimization Opportunities and Challenges in the Era of Slowing Silicon Process Technology
Chidi Chidambaram, Qualcomm -  VP Foundry Tech Development

Silicon process technology-based shrink, which has been slowing in the recent years, has led to growth in die size of most chipsets, including mobile. Splitting the die has become a mandatory practice and compute platforms, that are usually at larger sizes, have been leading the way. Mobile must follow suit. A system perspective, and sound architectural understanding, are essential to delivering the power and performance on these split die heterogeneous systems. Some of the challenges and opportunities of these heterogeneous integrations will be reviewed.

9:00am - 9:45am

KEYNOTE: Silicon SiPs for the Metaverse
Ron Ho, Meta - Senior Director of Silicon Engineering 

One of the enduring societal lessons of the past two years revolves around the fragility – and the deep importance – of personal and social engagement. At Meta’s Reality Labs we build tools that connect people and bridge distance, and we see that mission as increasingly relevant to tomorrow. The technical challenges in enabling AR and VR are immense, and many of the focus on the ecosystem around customized silicon. But with challenges come opportunities for innovation, and in this talk I will discuss some of our ideas.

Exhibit Tables open 9:45am - 6:30 pm

Session 1: 5G/Mobile

Chair: Steven Kummerl, Texas Instruments

Warpage Simulation and Measurement of a SIP Module for Laptop CPU Applications
Pouya Talebbeydokhti, Intel Corp.

Next generation RF Front End Based SiPs: Platform Needs, Features and Design Considerations 
Matthew Poulton, Qorvo

Lunch & Networking with Exhibitors

Thank you to our sponsor:

Flexing, Bending and Stretching to the Future of Wearable Medical Devices
Mark Poliks, Binghamton Univ.

Break - in Exhibitor Area

Thank you to our sponsor:

Tuesday Panel Session on
REMAINING CHALLENGES IN THE ADOPTION OF 5G

Moderator: Jan Vardaman, TechSearch International

The rollout of 5G is underway. A variety of substrate materials are used in 5G mmWave applications, including LTCC, flex circuit, and low-loss laminate substrates such as BT resin, FR-4, and build-up film. Polymer redistribution materials are used for WLP and glass is also an option. Liquid crystal polymer is used for the antenna in some applications. Will any one material dominate the package?  Will packages use antenna-in-package (AiP) or is antenna on chip (AoC) more common? Are there test issues with the different antenna designs? The panel will address these questions.

Matthew Poulton, Qorvo
Curtis Zwenger, Amkor Technology

Additional panelists soon

Exhibit Reception

Thank you to our sponsors:

8:00am - 8:45am

KEYNOTE: Trends and Reliability Challenges in Advanced Driving Assistance System (ADAS)
Khai Nguyen, NVIDIA

Fast changing in autonomous driving applications make the whole automotive industry becoming a transformation process. The car has become a product that integrates all possible variants of complex semiconductor-based functions from both HW and SW, including AI. The automotive industry now requires IC with high performance, low power, and made from resilience capable (fail operational) robust technologies. This likely introduces complexed pictures in aspects of HW/SW maintenance, safety, security, reliability, and cost. New challenges, thus, take places due to evolving complexity of IC construction and connection technologies. As a result, the impacts of additional challenges on reliability are enormous and need to be addressed. However, these challenges also provide opportunities for innovative thinking.

8:45am - 9:30am

Exhibit Tables open 9:30am - 3:30 pm

Lunch & Networking with Exhibitors

Thank you to our sponsor:

Session 4: Automotive & Power
Chair: Mathew Poulton, Qorvo

Packaging Technology for Automotive Power Delivery
Hongbin Yu, Arizona State University 

Assurance of Sustained High Temperature Reliability for Underfills and Interfaces in FCBGAs for Automotive Underhood Operation
Pradeep Lall, Auburn University

Exhibits close following Break

START-UP COMPETITION
Moderator: Jan Vardaman, TechSearch International

Thank you to our sponsor:

Start-up Companies:
Averatek
Avicena
Mosaic Microsystems
Sivers Semiconductors (Mixcomm)

The start-up competition session will feature brief presentations by each of the four start-up companies listed above, which will be evaluated by a panel of selected judges and a winning company will be selected during this live session. 

Panel Session on
CHIPLET BASED ARCHITECTURES - THE ROAD TO MASS ADOPTION 

Moderator: Eelco Bergman, ASE Group

As the semiconductor industry continues to advance its roadmap, we have started seeing a marked shift to chiplet based, heterogeneously integrated, silicon system architectures for a variety of reasons including performance, cost and yield optimization.  The initial implementations have been primarily by the leading semiconductor manufacturers and wafer foundries.  The advantages for cost/yield optimization, bandwidth, performance, latency, mixed technology integration, etc. are evident, so this panel will explore what’s going to be required for the industry to adopt this new design paradigm on a much broader scale.

Panelists: 
Lihong Cao, ASE Group
Kenneth Larsen, Synopsys
Khai Nguyen, nVidia
Robert Patti, Nhanced Semi.

Sip at SiP
Wine Tasting, Education & Networking

Thank you to our sponsor:

Appetizers and Snacks provided

Ticketed event only - select number of wine tickets as an add-on to your conference registration -  $50 per person

Purchase wine tickets - select # of wine tickets on page 2
Significant others, friends, non-attendees are welcome to join

Sip at SiP participants will enjoy a wine education experience led by Brian Schmaltz, tasting five delicious and unique wines, coupled with delicious food (artesian cheeses, vegetable crudite, various pastas, tri-tip steak, and more), all while networking with fellow conference attendees! Brian and Robin have hand-selected five incredible wines for you to enjoy:  AC Rosé made from 100% Pinot Noir Sangiacomo Vineyards 2021 Chardonnay Sangiacomo Vineyard  (Barrel Sample, to be bottled this Summer) 2021 Pinot Noir Signal Ridge Vineyard  (Barrel Sample, to be bottled this Summer) 2018 Volume VI Napa Cabernet Sauvignon Special Vintage Napa Cabernet Sauvignon
Library Collection Wine Fine Art & Wine.... There is nothing better. Limited each year to a different artist; a Volume, a one off, to be categorized in the Library never to be seen again. That is until you are ready to open a piece of history, time in a bottle. We feel every vintage is a different wine entirely, thus we decided that the label artwork to be representative of that, unique for every vintage. We call on artists whose work we admire to contribute as our label, changing year to year featured on our limited hand numbered production. Once they are gone, they are gone. Certain never to be repeated. Enjoy them for decades to come - Cheers, Robin Akhurst and Brian Schmaltz. Robin F. Akhurst ~Current winemaker at Apsara Cellars and Swanson Vineyards. Has had the privilege of working with Anne Claude Leflaive at Domaine Leflaive in Burgundy, Matt Wenk of Two Hands Wines in the Barossa, Thomas Rivers Brown of Schrader/Outpost Cellars and Mike Smith of Myriad /Carter Cellars in the Napa Valley. Some of the best winemakers/wines in the world. Brian T. Schmaltz ~Mechanical Engineer by trade, vintner by choice. Received his BS and MS in Mechanical Engineering from San Diego State University with a specialization in FEM and MEMS processing. In his spare time he enjoys blending, waxing, labeling, sorting, pump overs, and punch downs.

7:00am - 8:00am

8:15am - 9:00am

KEYNOTE: Conducting the Semiconductors: The Role of Design in the SysMoore Era
Ming Zhang, Synopsys - Distinguished Architect

As manufacturing technology around advanced packaging evolves, the performance and density of designs being enabled have experienced tremendous advancement in the past decade. The next decade is the time for the EDA industry to give wings to chip and system designers of the SysMoore era.  In this talk, we will introduce the roles of design elements such as die-to-die interface IP, end-to-end EDA automation, and test / debug / life cycle management play in advanced packaging. We will also discuss some future challenges in complexity of design, verification, and security. 

What‘s the Future of Final Test?
Ken Lanier, Teradyne

Closing Remarks