SiP Agenda


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The top global virtual event for Advanced System-in-Package technologies!
Combining the 3D ASIP and IMAPS SiP events into an exciting, comprehensive program:

One event covering SiP technology developments, solutions and business trends.

Monday, June 20th | 9:00am-12:30pm

Heterogeneous Integration Roadmap (HIR) Workshop

The  Heterogeneous Integration Roadmap (HIR) is a roadmap to the future of electronics identifying technology requirements and potential solutions. The primary objective is to stimulate pre-competitive collaboration between industry, academia and government to accelerate progress. The roadmap offers professionals, industry, academia and research institutes a comprehensive, strategic forecast of technology over the next 15 years. The HIR also delivers a 25-year projection for heterogeneous integration of Emerging Research Devices and Emerging Research Materials with longer research-and-development timelines. The HIR is sponsored by three IEEE Societies (Electronics Packaging Society, Electron Devices Societry & Photonics Society) together with SEMI and ASME Eeelctronics & Photonics Packaging Division.  

HIR Agenda:

9:00 am – 9:15 am              
HIR Session Introduction: Mark Gerber, SiP General Chair and Bill Chen HIR Introduction

9:15 am – 9:40 am
HIR Overview
Bill Chen, ASE

9:45 am – 10:05 am
Integrated Photonics
Bill Bottoms, 3MTS

10:05 am – 10:30 am
Automotive Electronics
Vikas Gupta, ASE

10:30 am - 11:00 am -- BREAK

11:00 am – 11:25 am
Thermal Management
Mehdi Asheghi, Stanford University

11:25 am – 11:50 am
Supply Chain
Thomas Gregorich, Infinera

11:50 am – 12:15 pm
HIR Workshop Final Question & Closing Remarks
Bill Chen, ASE

12:15 pm - 1:00 pm -- HIR WORKSHOP LUNCH

PDC Courses

1:00pm - 2:45pm
PDC 1: 3D Package Assembly Processes and Technology 
Tom Dory, Fujifilm Electronic Materials USA
PDC 2: System-in-Package (SiP) - System Solutions Through Miniaturization 
Mark Gerber, ASE US, Inc.
2:45pm - 3:15pm


3:15pm - 5:00pm

PDC3: Chiplet Design and Heterogeneous Integration Packaging 
John H. Lau, Unimicron Technology Corporation

Tuesday, June 21st

7:00am - 8:00amBreakfast
8:00am - 8:15amOpening RemarksMark Gerber, ASE US, Inc.

8:15am - 9:00am

Chidi Chidambaram

KEYNOTE: System-level Optimization Opportunities and Challenges in the Era of Slowing Silicon Process Technology
Chidi Chidambaram, Qualcomm -  VP Foundry Tech Development

Silicon process technology-based shrink, which has been slowing in the recent years, has led to growth in die size of most chipsets, including mobile. Splitting the die has become a mandatory practice and compute platforms, that are usually at larger sizes, have been leading the way. Mobile must follow suit. A system perspective, and sound architectural understanding, are essential to delivering the power and performance on these split die heterogeneous systems. Some of the challenges and opportunities of these heterogeneous integrations will be reviewed.


9:00am - 9:45am

KEYNOTE: Silicon SiPs for the Metaverse
Ron Ho, Meta - Senior Director of Silicon Engineering 

One of the enduring societal lessons of the past two years revolves around the fragility – and the deep importance – of personal and social engagement. At Meta’s Reality Labs we build tools that connect people and bridge distance, and we see that mission as increasingly relevant to tomorrow. The technical challenges in enabling AR and VR are immense, and many of the focus on the ecosystem around customized silicon. But with challenges come opportunities for innovation, and in this talk I will discuss some of our ideas.

9:45am - 10:30amBreak in Exhibit Area

Exhibit Tables open 9:45am - 6:30 pm

Session 1: 5G/Mobile

Chair: Steven Kummerl, Texas Instruments

10:30am -11:00am

Warpage Simulation and Measurement of a SIP Module for Laptop CPU Applications
Pouya Talebbeydokhti, Intel Corp.

11:00am - 11:30am

Next generation RF Front End Based SiPs: Platform Needs, Features and Design Considerations 
Matthew Poulton, Qorvo

11:30am - 12:00pmMulti-terminal thin Silicon Capacitors enabling best in-package decoupling strategy for Mobile and HPC
Mohamed Jatlaoui, Murata

12:00pm - 1:30pm

Lunch & Networking with Exhibitors

Thank you to our sponsor:
ASE Group

Session 2: Wearables/IoT
Chair: Bob Patti, Nhanced

1:30pm - 2:00pmEmpowering Front-End Cellular Innovations with Advanced SiP Solutions
Curtis Zwenger, Amkor Technology

2:00pm - 2:30pm

Flexing, Bending and Stretching to the Future of Wearable Medical Devices
Mark Poliks, Binghamton Univ.

2:30pm - 3:00pmInnovative Materials for Advanced Packaging and System in Package (SiP)
Szi Pei LIm, Indium Corp. (Dongkai Shangguan)

3:00pm - 4:00pm

Break - in Exhibitor Area

Thank you to our sponsor:

4:00pm - 5:30pm

Tuesday Panel Session on

Moderator: Jan Vardaman, TechSearch International

The rollout of 5G is underway. A variety of substrate materials are used in 5G mmWave applications, including LTCC, flex circuit, and low-loss laminate substrates such as BT resin, FR-4, and build-up film. Polymer redistribution materials are used for WLP and glass is also an option. Liquid crystal polymer is used for the antenna in some applications. Will any one material dominate the package?  Will packages use antenna-in-package (AiP) or is antenna on chip (AoC) more common? Are there test issues with the different antenna designs? The panel will address these questions.

Mark Gerber, ASE US

Matthew Poulton, Qorvo
Curtis Zwenger, Amkor Technology

Additional panelists soon

5:30pm - 6:30pm

Exhibit Reception

Thank you to our sponsors:


Wednesday, June 22nd

7:00am - 8:00amBreakfast
8:00am - 8:15amOpening Remarks: Steven Kummerl, Texas Instruments

8:00am - 8:45am

KEYNOTE: Trends and Reliability Challenges in Advanced Driving Assistance System (ADAS)
Khai Nguyen, NVIDIA

Fast changing in autonomous driving applications make the whole automotive industry becoming a transformation process. The car has become a product that integrates all possible variants of complex semiconductor-based functions from both HW and SW, including AI. The automotive industry now requires IC with high performance, low power, and made from resilience capable (fail operational) robust technologies. This likely introduces complexed pictures in aspects of HW/SW maintenance, safety, security, reliability, and cost. New challenges, thus, take places due to evolving complexity of IC construction and connection technologies. As a result, the impacts of additional challenges on reliability are enormous and need to be addressed. However, these challenges also provide opportunities for innovative thinking.

8:45am - 9:30am

KEYNOTE: Automotive Packaging Ecosystem
Anindya Poddar, Texas Instruments

9:30am - 10:15amBreak in Exhibits Area

Exhibit Tables open 9:30am - 3:30 pm

Session 3: HPC/SiP 
Chair: Eelco Bergman, ASE Group

10:15am - 10:45amThe Path to a Sub fJ/bit Interconnect
Daniel Graf, Zero EC

10:45am - 11:15amAdvanced Fanout Embedded Bridge Packaging Technology for Chiplets Integration
Lihong Cao, ASE Group

11:15am - 11:45amHybrid Bonding - A Key to the Future
Robert Patti, Nhanced Semi.

11:45am - 1:15pm

Lunch & Networking with Exhibitors

Thank you to our sponsor:

Session 4: Automotive & Power
Chair: Mathew Poulton, Qorvo

1:15pm - 1:45pm

Packaging Technology for Automotive Power Delivery
Hongbin Yu, Arizona State University 

1:45pm - 2:15pm

Assurance of Sustained High Temperature Reliability for Underfills and Interfaces in FCBGAs for Automotive Underhood Operation
Pradeep Lall, Auburn University

2:15pm - 2:45pmPackaging Technology for Beyond 100kW/L
Mike Marczi, Marel Power

2:45pm - 3:30pmBreak - In Exhibitor Area

Exhibits close following Break

3:30pm - 5:00pm

Moderator: Jan Vardaman, TechSearch International

Thank you to our sponsor:

Start-up Companies:
Mosaic Microsystems
Sivers Semiconductors (Mixcomm)

The start-up competition session will feature brief presentations by each of the four start-up companies listed above, which will be evaluated by a panel of selected judges and a winning company will be selected during this live session. 

5:00pm - 6:30pm

Panel Session on

Moderator: Eelco Bergman, ASE Group

As the semiconductor industry continues to advance its roadmap, we have started seeing a marked shift to chiplet based, heterogeneously integrated, silicon system architectures for a variety of reasons including performance, cost and yield optimization.  The initial implementations have been primarily by the leading semiconductor manufacturers and wafer foundries.  The advantages for cost/yield optimization, bandwidth, performance, latency, mixed technology integration, etc. are evident, so this panel will explore what’s going to be required for the industry to adopt this new design paradigm on a much broader scale.

Lihong Cao, ASE Group
Kenneth Larsen, Synopsys
Khai Nguyen, nVidia
Robert Patti, Nhanced Semi.

6:30pm - 8:00pm

Sip at SiP
Wine Tasting, Education & Networking

Thank you to our sponsor:
Amkor Technology

Appetizers and Snacks provided

Ticketed event only - select number of wine tickets as an add-on to your conference registration -  $50 per person

Purchase wine tickets - select # of wine tickets on page 2
Significant others, friends, non-attendees are welcome to join

Library Wine Collection

Sip at SiP participants will enjoy a wine education experience led by Brian Schmaltz, tasting five delicious and unique wines, coupled with delicious food (artesian cheeses, vegetable crudite, various pastas, tri-tip steak, and more), all while networking with fellow conference attendees! Brian and Robin have hand-selected five incredible wines for you to enjoy: 

  1. AC Rosé made from 100% Pinot Noir Sangiacomo Vineyards
  2. 2021 Chardonnay Sangiacomo Vineyard  (Barrel Sample, to be bottled this Summer)
  3. 2021 Pinot Noir Signal Ridge Vineyard  (Barrel Sample, to be bottled this Summer)
  4. 2018 Volume VI Napa Cabernet Sauvignon
  5. Special Vintage Napa Cabernet Sauvignon

Library Collection Wine

Fine Art & Wine.... There is nothing better. Limited each year to a different artist; a Volume, a one off, to be categorized in the Library never to be seen again. That is until you are ready to open a piece of history, time in a bottle. We feel every vintage is a different wine entirely, thus we decided that the label artwork to be representative of that, unique for every vintage. We call on artists whose work we admire to contribute as our label, changing year to year featured on our limited hand numbered production. Once they are gone, they are gone. Certain never to be repeated.

Enjoy them for decades to come - Cheers, Robin Akhurst and Brian Schmaltz.

Robin F. Akhurst ~Current winemaker at Apsara Cellars and Swanson Vineyards. Has had the privilege of working with Anne Claude Leflaive at Domaine Leflaive in Burgundy, Matt Wenk of Two Hands Wines in the Barossa, Thomas Rivers Brown of Schrader/Outpost Cellars and Mike Smith of Myriad /Carter Cellars in the Napa Valley. Some of the best winemakers/wines in the world.

Brian T. Schmaltz ~Mechanical Engineer by trade, vintner by choice. Received his BS and MS in Mechanical Engineering from San Diego State University with a specialization in FEM and MEMS processing. In his spare time he enjoys blending, waxing, labeling, sorting, pump overs, and punch downs.

Library Wine Collection

Robin and Brian

Thursday, June 23rd

7:00am - 8:00am


8:15am - 9:00am

KEYNOTE: Conducting the Semiconductors: The Role of Design in the SysMoore Era
Ming Zhang, Synopsys - Distinguished Architect

As manufacturing technology around advanced packaging evolves, the performance and density of designs being enabled have experienced tremendous advancement in the past decade. The next decade is the time for the EDA industry to give wings to chip and system designers of the SysMoore era.  In this talk, we will introduce the roles of design elements such as die-to-die interface IP, end-to-end EDA automation, and test / debug / life cycle management play in advanced packaging. We will also discuss some future challenges in complexity of design, verification, and security. 

Session 5: EDA/Design
Chair: Curtis Zwenger, Amkor Technology

9:00am - 9:30amDesign and Analysis Challenges for Multi-chiplet 3D Integration
John Park, Cadence

9:30am - 10:00amEnabling a Chiplet based Ecosystem
Anthony Mastroianni, Siemens

10:00am - 10:45amBreak 
Session 6:  Test / Inspection
Chair: Habib Hichri, Ajinomoto

10:45am - 11:15amTest Impact of Chiplets in Packages
Warren Wartell, Amkor Technology

11:15am - 11:45am5G RF Front End System in Package(SiP) Test ChallengesD
Wei Wang, NI 

11:45am - 12:15pm

What‘s the Future of Final Test?
Ken Lanier, Teradyne


Closing Remarks