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The Westin Arlington | Arlington, VA
www.imaps.org/onshoring
Workshop registration restricted to U.S. Passport Holders Only
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Premier Sponsor
Exhibitors
ENGENT - Enabling Next Gen Technology
IBM
Keysight Technologies
MRSI Mycronic
Neutronix Quintel
Silitronics
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| ONSHORING COMMITTEE
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| General Chair: Brandon Hamilton, BAE Systems Inc
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Technical Chair: Ted Tessier, IBM
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Organizing Committee
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Steve Dooley, AFRL | Phil Garrou, Microelectronics Consultants of NC
Brandon Hamilton, BAE Systems, Inc. | Darrick Korte, NSWC Crane | T
imothy Morgan, NSWC Crane | Brian Olson, NSWC Crane
Christopher Riso, Booz Allen Hamilton | Michael D. Sinanis, NSWC Crane |
Bryan Smith, NSWC Crane | Ted Tessier, IBM
Matt Walsh, NSWC Crane | Jim Will, SkyWater Technologies
IMAPS: Brian Schieman, Kristie Bowman | IPC: Matt Kelly
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Overview: The International Microelectronics Assembly and Packaging Society (IMAPS) and IPC will host a three-day Workshop to discuss and promote strategies to improve On-Shoring Advanced Packaging and Assembly, April 29 - May 1, 2024,
at The Westin Arlington, Arlington, VA. This workshop will be bringing Government agencies, the DIB (Defense Industrial Base) and Advanced Packaging and Assembly providers together to discuss their efforts to onshore advanced
packaging. The mission of this workshop is to engage our workforce community to identify the newly created Advanced Packaging programs which address US Government and Defense requirements critical to the onshoring of the microelectronic
assembly and packaging supply chain. Government agencies including the Department of Commerce/NIST, DoD (SHIP/IBAS/Title III), and DARPA will be briefing on their advanced packaging programs.
The workshop will feature three days of focused sessions, keynote presentations, a panel discussion, and a variety of networking opportunities. The event will kick-off on Monday with a pre-program day filled with 2-hour professional development courses and/or additional working groups addressing a variety of topics relevant to the onshoring of advanced packaging. The 2024 Workshop will also feature networking opportunities with sponsors and tabletop exhibitors.
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| PROGRAM
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| Monday, April 29 |
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7:00AM - 6:00PM
Registration Opens
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7:00AM - 8:00AM
Continental Breakfast
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12:00PM - 5:00PM
EXHIBITS OPEN
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8:00AM-9:45AM PROFESSIONAL DEVELOPMENT COURSE (Additional Registration Fee Below)
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PDC 1: Introduction to Packaging & System-in-Package (SiP) - System Solutions Through Miniaturization - Mark Gerber
This PDC course will introduce packaging and the package platform SiP (System-in-Package) and how some companies are diversifying for SOC (System-on-a-Chip) to leverage heterogeneous sililcon integration and package miniaturization to enable system level solutions. A short market perspective will be reviewed as well as how industry segments are leveraging SiP and how the OEM market is evolving and creating system level ecosystems to enablig content revenue - a key area of IOT (Internet of Things). The SIP Platform uses many assembly processes from various package platforms that make up the complete toolbox - thus we will provide an introduction to basic packaging as well. SiP general process flow details will be covered as well as key process considerations for yield improvements. In addition, a brief overview of some of the tools that may be leveraged to help miniaturize module solutions and improve performance. This class will also introduce several variations of the SIP platform using Fan-Out Wafer Level packaging and new embedded substrate technologies are also emerging as powerful future platforms to enable lower power and higher performance devices using solderless interconnects. |
9:45AM - 10:15AM
BREAK
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10:15AM-12PM PROFESSIONAL DEVELOPMENT COURSES (Please choose 1 Course - Additional Registration Fee Below)
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PDC 2: Chiplet Design and Heterogenous Integration Packaging - John Lau
Chiplet is a chip design method and heterogeneous integration is a chip packaging method. Chiplet design and heterogeneous integration packaging have been generated lots of tractions lately. For the next few years, we will see more implementations of a higher level of chiplet designs and heterogeneous integration packaging, whether it is for cost, time-to-market, performance, form factor, or power consumption. In this lecture, the following topics will be covered.
- System-on-Chip (SoC)
- Why Chiplet Design?
- Chiplet Design and Heterogeneous Integration Packaging – Chip Partition and Chip Split
- Chip partition and Heterogeneous Integration
- Chip split and Heterogeneous Integration
- Advantages and Disadvantages
- Communication between Chiplets (e.g., Bridges)
- Bridge Embedded in Build-up Package Substrate
- Bridge Embedded in Fan-Out EMC with RDLs
- UCIe
- Hybrid Bonding Bridge
- Chiplet Design and Heterogeneous Integration Packaging - Multiple System and Heterogeneous Integration
- Multiple System and Heterogeneous Integration with Package Substrate (2D IC Integration)
- Multiple System and Heterogeneous Integration with Thin Film layer on the Package Substrate (2.1D IC Integration)
- Multiple System and Heterogeneous Integration with TSV-less (Organic) Interposer (2.3D IC Integration)
- Multiple System and Heterogeneous Integration with Passive TSV-Interposer (2.5D IC Integration)
- Multiple System and Heterogeneous Integration with Active TSV-Interposer (3D IC Integration)
- Advanced Packaging Driving by Artificial Intelligent
- Co-Packaged optics
- Summary
- Potential R&D Topics in Chiplet Design and Heterogeneous Integration Packaging
- Trends in Chiplet Design and Heterogeneous Integration Packaging
Who Should Attend?
If you (students, engineers, and managers) are involved with any aspect of the electronics industry, you should attend this course. It is equally suited for R&D professionals and scientists. The lectures are based on the publications by many distinguish authors and the books by the lecturer.
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PDC 3: Advanced Fanout Structures, Processes, and Applications - John Hunt
Basic Fan Out technology was developed over 15 years ago as a simple way to expand the available surface area for the I/O solder balls as die shrank in size. This simple Fan Out technology has evolved into an advanced packaging technology to meet both the need for miniaturization of electronics, using low density Fan Out; and for the interconnectivity of complex packages such as chiplet using more advanced Fan Out assemblies. The increased use of mobile and IOT for communication and entertainment has driven the need for increased capability of data centers and mobile computing systems. Fan Out technology is currently evolving in complexity and capability for many of these applications. It enables the heterogeneous integration of multiple application die and memory die with improved electrical performance and lower cost than traditional high-density packaging such as 2.5D interposer packaging. Emerging high-performance computing applications will increasingly use Fan Out. We will review how these new Fan Out structures and processes, together with Flip Chip packaging and advanced substrates have combined to enable advances in current and future complex Fan Out packaging. These packaging technologies are being used for a wide variety of automotive, mobile, server and AI applications.
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12:00PM - 1:00PM
LUNCH & EXHIBITS
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1:00PM - 1:30PM
Opening Remarks
Brandon Hamilton and Ted Tessier
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1:30PM - 2:00PM
KEYNOTE:
Adele Ratcliff, Director of the Innovation Capability and Modernization (ICAM) Office
TOPIC:
Status of IBAS Packaging Programs
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Ms. Adele Ratcliff is the Director of the Assistant Secretary of Defense for Industrial Base Policy’s Innovation Capability and Modernization office. In this position, she implements the broad authorities of the Industrial Base Analysis and Sustainment (IBAS) Program to strengthen the competitive posture of the U.S. Defense Industrial Base by fortifying traditional technical capabilities and forging emerging industrial sectors to respond at-will to national security requirements. She has been an industrial base champion leading transformative initiatives including developing manufacturing readiness levels, inspiring movement to the digital thread, spearheading the DoD Manufacturing USA institutes, establishing America’s Cutting Edge (ACE) in partnership with the Dept of Energy to catalzye the U.S. machine tool industry, and leading the DoD to focus efforts to regrow a strong manufacturing trades capability.
Ms. Ratcliff has served as Director of the DoD Manufacturing Technology (ManTech) Program, Program Manager for the congressionally mandated Defense Acquisition Challenge Program, Deputy Program Manager for the Foreign Comparative Test Program, and 11+ years in Air Force Test and Evaluation at Eglin Air Force Base where she was awarded Civilian Test Engineer of the Year. She
is an alumnus of the Mississippi State University Bulldogs, earning a BS in Mechanical Engineering. In 2011 she graduated from the U.S. Army War College earning an MS in Strategic Art, and is a graduate of the
Department of Defense’s Defense Senior Leadership Development Program.
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Session 1
RESHAPE
Session Chair: Matt Walsh, NSWC Crane
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2:00PM - 2:30PM
Introduction of Presenters Highlighting RESHAPE Elements
Matt Walsh, NSWC Crane
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2:30PM - 3:00PM
Bridg/Skywater (Si Interposer Standup and IMEC Transfer to Bridg/Skywater)
John Algair, Bridg/Skywater
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3:00PM - 3:30PM
Establishing Advanced Fan-Out Capability in the U.S. - The SkyWater/Osceola County eFOCUS Program
Alan Huffman, Bridg/Skywater
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3:30PM - 4:00PM
BREAK & EXHIBITS
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4:00PM - 4:30PM
Micross 300mm Wafer Prep and Bumping Standup
John Lannon, Micross
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4:30PM - 5:00PM
KEYNOTE:
Dr. Dev Palmer, Next-Generation Microelectronics Manufacturing (NGMM) Program Managing Director, DARPA
TOPIC: NGMM at DARPA
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Dev Palmer is Managing Director, Next-Generation Microelectronics Manufacturing (NGMM) at the DARPA Microsystems Technology Office. Previously he served as MTO Deputy Director. Prior to joining DARPA, he was Chief Technologist at Lockheed Martin Advanced Technology Laboratories where he directed the independent research and development program and implemented technology strategy.
Earlier in his career he directed a portfolio of programs ranging from basic research to advanced technology transition in Program Manager roles at DARPA and the Army Research Office. Dr. Palmer is a Life Fellow of the IEEE, author on over 125 publications in print and electronic media, and inventor on four US patents.
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Session 2
Title III
Session Chair: Steve Dooley, AFRL
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5:00PM - 5:30PM
On-Shoring Organics Substrates (HDBU) - DPA Title 3 Investment with Calumet Electronics
Meredith LaBeau, Calumet Electronics
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5:30PM - 6:00PM
DPA Title III Expansion Update
Michael Gleason, GreenSource
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| Tuesday, April 30
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7:00AM - 6:30PM
Registration Open
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7:00AM - 8:00AM
Breakfast
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8:00AM - 8:15AM
Opening Remarks
Brandon Hamilton and Ted Tessier
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8:15AM - 8:45 AM
KEYNOTE: Dr. Dev Shenoy, Principal Director for Microelectronics - Office of the Undersecretary of Defense, Director of the Defense Microelectronics Cross Functional Team
TOPIC: OUSD R&E Efforts
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Dr. Dev Shenoy joined the Office of the Under Secretary of Defense for Research and Engineering, OUSD(R&E) in July 2021, where he serves as the Principal Director for Microelectronics. In this Dr. Shenoy is responsible for leading the Department of Defense (DoD) research and engineering efforts in microelectronics and serving as the point of coordination for development of a holistic DoD microelectronics strategy. In
support of DoD’s Microelectronics outreach strategy, Dr. Shenoy has provided over 50 keynote briefings and interviews across a broad range of commercial, academic, interagency and defense communities. Prior to joining
OUSD(R&E), Dr. Shenoy served as the Director of Microelectronics Innovation and as Director of Advanced Technologies at the University of Southern California’s Information Sciences Institute, Chief Engineer in the
Advanced Manufacturing Office at the Department of Energy, and a Program Manager at DARPA. Dr. Shenoy has a Ph.D. in Physics from the prestigious Indian Institute of Science in Bangalore, India, and
NSF postdoctoral experience from Case Western Reserve University in Cleveland, Ohio.
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Session 3
Trusted and Assured Microelectronics
Session Chair: Brian Olson, NSWC Crane
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8:45AM - 9:15AM
SHIP Digital Overview and Transition Strategy and Execution
Brian Olson, NSWC Crane
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9:15AM - 9:45AM
Challenges and Lessons on Maturing Advanced Packaging for Production
Tom Rucker, Intel ATTD
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9:45AM - 10:30AM
BREAK & EXHIBITS
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9:30AM - 6:30PM
EXHIBITS OPEN
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10:30AM - 11:00AM
SHIP Update MCP 1-4 Overview and Release Schedule
Carmine Pagano, Altera
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11:00AM - 11:30AM
SHIP RF History, Overview and Evolution
Michael Sinanis, NSWC Crane
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11:30AM - 12:00PM
SHIP RF and Advanced RF Packaging Update
Ted Jones, Qorvo
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12:00PM - 1:00PM
LUNCH & EXHIBITS
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1:00PM - 1:30PM
KEYNOTE: Dr. George Orji -
Deputy Director, CHIPS NAPMP
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George Orji is the Deputy Director of CHIPS NAPMP, within CHIPS R&D Office. Prior to this role, he was a Senior Program Advisor in the CHIPS R&D Office, and before then a Program Analyst in the NIST Program Coordination Office, in the Office of the NIST Director. In that role, he provided technical program and policy analysis, worked with line organizations and other staff offices on planning NIST-level strategies, program evaluation, policy coordination, budget and program initiatives, including early CHIPS Act implementation planning.
He spent more than 15 years in the NIST Labs as a project leader and mechanical engineer in the Physical Measurement, and Manufacturing Engineering Laboratories, where he led projects on nanoscale dimensional metrology, probe-based instrument and measurement methods development, uncertainty analysis, and standards development. He received his PhD in mechanical engineering from the University of North Carolina at Charlotte and is a Senior Member of both IEEE and SPIE.
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Session 4
DIB Session #1
Session Chair: Darrick Korte, NSWC Crane
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1:30PM - 1:50PM
BAE Presentation - SHIP RF & Digital/STAMP/STEAM PIPE 23
Kim Eilert, BAE
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1:50PM - 2:10PM
NG Presentation - SHIP RF/STAMP v2/STEAM PIPE 23
Dave Shahin, Northrop Grumman
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2:10PM - 2:30PM
Marvell Presentation - STEAM PIPE 23
Angela Weil, Marvell |
2:30PM - 2:50PM
Raytheon Presentation - SHIP Digital/STAMP v2/STEAM PIPE 23 x 2
Ted Hoffman, Raytheon
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2:50PM - 3:30PM
BREAK & EXHIBITS
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3:30PM - 4:00PM
KEYNOTE: Joshua T. Hawke, PhD
Radio Frequency and Optoelectronics Lead
Naval Surface Warfare Center, Crane Division, (NSWC Crane)
TOPIC: RF/OE Initiatives
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Over the last decade, Dr. Joshua Hawke has led the authorship and execution of the DoD Microelectronics Roadmap for “Beyond CMOS” technologies. He is currently the Radio Frequency (RF) and Optoelectronics Execution Lead within OUSD(R&E)’s Trusted & Assured Microelectronics program. His primary portfolio goals are as follows: (1) maturation of mmW RF GaN foundries with advanced interconnect, (2) insertion of N-Polar GaN material into production-volume foundries, (3) maturation of co-packaged optics, (4) demonstration of high-performance transceivers and high-power computing, and (5) development of Power SiC technology for DoD applications. Additionally, he serves as the Portfolio Manager of RF & Optoelectronics for the Radar Technologies Division at the Naval Surface Warfare Center Crane, where the focus of his research targets the co-design of RF and power electronics for advanced sensor and communication systems. As a grateful recipient of the DoD SMART Scholarship, Joshua received his Ph.D. in Electrical Engineering from Texas A&M University in 2014.
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Session 5
DIB Session #2
Session Chair: Chris Riso, Booz Allen Hamilton
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4:00PM - 4:20PM
LM - SHIP Digital / STAMP v2
Dave Pawlowicz, LM
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4:20PM - 4:40PM
STAMP Performer Update: SWaP Reduction Benefits Using MCP1
Fred Ilsemann, Banc3
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4:40PM - 5:00PM
Boeing - STAMP v2
Rosa Lahiji, Boeing |
5:30PM - 7:00PM
Welcome Reception in Exhibit Area
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| Wednesday, May 1
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7:00AM - 2:00PM
Registration Open
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7:00AM - 8:00AM
Breakfast
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8:00AM - 8:15AM
Opening Remarks
Brandon Hamilton and Ted Tessier
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8:15AM - 8:45AM
KEYNOTE:
Dr. Eric Lin, Deputy Director, CHIPS Research and Development Program
TOPIC: CHIPS R&D: Progress to Date and Next Steps
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Until joining the CHIPS for America R&D Program in an interim role, Lin was Director of the Material Measurement Laboratory (MML) at the National Institute of Standards and Technology (NIST). MML has 900+ staff members and visiting scientists and serves as the nation's reference laboratory for measurements in the chemical, biological and materials sciences.
Lin has also served as the Acting Associate Director for Laboratory Programs at NIST. In this role, he provided direction and operational guidance for all of NIST's scientific and technical laboratory, among other duties.
Lin joined NIST as an NRC-NIST postdoctoral associate in the Polymers Division in the Materials Science and Engineering Laboratory. He became Electronics Group Leader, where he established world class research programs in semiconductor electronics processing, nanoscale materials, and organic electronics. In 2012, he became Chief of the Materials Science and Engineering Division. Lin’s work has supported important technology areas including advanced manufacturing and advanced electronics, and the multi-agency Materials Genome Initiative. He's been active in several cross-NIST programs, serving on the NIST Incentive Awards Panel, the NIST-on-a-Chip Committee, and the NIST Strategic Computing Initiative Committee.
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Session 6
Workforce Development
Session Chair: Shubhra Bansal
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8:45AM - 9:05AM
SCALE
Shubhra Bansal, Purdue University
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9:05AM - 9:25AM
Intel's Semiconductor Education and Research Program
Sowmya Venkatramani, Intel
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9:25AM - 9:45AM
Arizona Manufacturing Institute - AzAMI at the Maricopa Community Colleges District
Leah Palmer, MCCD
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9:45AM - 10:05AM
Workforce Development Initiatives at ME Commons
Erin Gawron-Hyla, Army
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9:30AM - 1:00PM
EXHIBITS OPEN
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10:05AM - 10:30AM
BREAK & EXHIBITS
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Session 7
Chiplet Session
Session Chair: Jim Will, Skywater
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10:30AM - 10:50AM
Cadence
Darin Heckendorn, Cadence
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10:50AM - 11:10AM
Zero Asic
Andreas Olofsson, Zero Asic
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11:10AM - 11:30AM
Synopsys
Ken Potts, Snynosys
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11:30AM - 12:30PM
LUNCH & EXHIBITS
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12:30PM - 1:00PM
KEYNOTE: Molly Just - Director of CHIPS Coordination Cell, OUSD A&S
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Session 8
ME Commons Activity
Session Chair: Dr. Tim Morgan, NSWC Crane
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1:00PM - 1:15PM
ME COMMONS Overview
Dr. Tim Morgan, NSWC Crane
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1:15PM - 1:25PM
CTEA Lead 5G/6G
Eric Makara, Navy
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1:25PM - 1:35PM
CTEA Lead AI Hardware
John Hodapp, Army
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1:35PM - 1:45PM
CTEA Lead Commercial Leap Ahead
Fritz Kub, NRL
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1:45PM - 1:55PM
CTEA Lead EW
Ali Darwish, Army
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1:55PM - 2:05PM
CTEA Lead Quantum
Mike Fanto, AFRL
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2:05PM - 2:15PM
CTEA Lead Secure Edge/loT
Christopher Morris, Army
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2:15PM - 2:45PM
ME Commons Q&A Combined all CTEA Leads & Tim Morgan
Panel Format
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2:45PM - 3:00PM
Closing Remarks
Brandon Hamilton |
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REGISTRATION
(IMAPS CAGE Code: 88HF3)
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Workshop registration restricted to
U.S. Passport Holders Only |
Early (on or before APRIL 10)
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After APRIL 10
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| IMAPS / IPC Member Attendee |
$695 |
$795 |
| Nonmember Attendee |
$895 |
$995 |
| Speaker or Chair |
$349 |
$449 |
| Academic Faculty |
$349 |
$449 |
| PDC Courses (separate fee) |
$325 |
$325 |
Exhibition & Sponsorship:
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Tabletop Exhibit – IMAPS/IPC
Members
(Includes: 1 exhibit personnel badge with meals; additional discounted exhibit
badges at $150/person with meals, full session badges at $350/person)
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$795 |
$895 |
Tabletop Exhibit – Non-Members
(Includes: 1 exhibit personnel badge with meals; additional discounted exhibit
badges at $150/person with meals, full session badges at $350/person)
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$895 |
$995 |
Premier Sponsorship (limit 4)
(Includes: 1 six-foot tabletop exhibit; 2 exhibit personnel badges and 2 sessions badges; full-page print advertisement in the final program; video advertisement (youtube link) in the web final program; logo on event webpages/program/signage/promotions; additional discounted exhibit badges at $150/person with meals, full session badges at $350/person) |
$3000 |
$3500 |
Corporate Sponsorship (limit 6)
(Includes: 1 six-foot tabletop exhibit; 1 exhibit personnel badge and 1 session
badge; logo on event webpages/program/ signage/promotions; additional
discounted exhibit badges at $150/person with meals, full session badges at
$350/person)
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$1500 |
$2000 |
Add-on to your registration above:
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PDC Courses (separate fee) *Please choose 1 course*
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$325 per PDC |
$325 per PDC |
HOW TO REGISTER:
IMAPS MEMBERS
1. If you are a member of IMAPS, go to www.imaps.org
and log in with your username and password. If you do not know your username, email kobrien@imaps.org.
If you have forgotten your password, click Forgot your password? to receive a link to reset your password. Logging in before registering gives access to member pricing and saves having to enter your contact information.
2. Click on REGISTER above or from the event homepage.
3. Complete your registration.
NONMEMBERS
1. Click on REGISTER above.
2. Complete your registration.
CANCELLATION POLICY:
Cancellations must be received in writing. Cancellations received on or before April 9, 2024 will be refunded in full minus $100 processing fee. Cancellations received after April 9, 2024, will not be refunded under any circumstances. However, an attendee may request to transfer registration for the event to another prospective attendee at any point prior to April 29, 2024 with proper written notification provided to IMAPS. To request a transfer, please notify IMAPS at info@imaps.org.
NOTICE OF FILMING AND PHOTOGRAPHY
This Workshop may have a professional photographer and videographer filming at the event. By participating in this event, you give IMAPS the right to use photographs or video recordings taken of you for educational or promotional purposes and for possibly sharing on social media and the IMAPS website.
| HOTEL
RESERVATIONS
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Hotel reservation deadline: April 15, 2024. Please book your room(s) directly with The Westin Arlington Gateway Hotel listed below as soon as possible. The discounted hotel block is expected to sell out early.
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The Westin Arlington
801 North Glebe Road, Arlington, VA, 22203
(703) 717-6200
$265 / night
CLICK HERE FOR RESERVATIONS
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