Live Virtual Workshop on Advanced System-in-Pack
IMAPS Live Virtual Workshop on
ENABLING A PATH TO SYSTEM LEVEL SOLUTIONS
Wednesday, November 18, 2020 | 11:00am-2:15pm EASTERN | MS Teams
This workshop has been recorded. The recording and presentation files have been archived for workshop attendees only. Contact firstname.lastname@example.org for more information!
Power, Performance and expanded functionality are all driving factors in considering a higher level integrated device solutions. Today, more and more companies are looking for ways to differentiate themselves by providing more integrated silicon solutions but with the flexibility of integrating different silicon nodes, and other complementary devices. This workshop will allow some leading industry experts to talk about several key contributors to enabling more integrated solutions through design, materials and packaging. IMAPS is excited to provide this focused workshop as a pre-cursor to the 2021 Advanced SiP Conference being planned for next year. We look forward to your participation.
Workshop Program (Subject to Change):
General Chair: Mark Gerber, ASE Group
|11:15am-11:40am||Increase Power Density and Simplify Designs Using 3-D SiP Modules|
Today, designers are demanding an overall form-factor reduction to save board space, increase functionality, and allocate more circuit board real estate toward end-user applications – all with less space allocated to power management where not just the X-Y shrink but the 3D volumetric shrink is required. For example, in today’s Telecommunications Cloud Infrastructure systems, board space and power density are challenging particularly in power supply designs where several high-current point-of- load rails are present. End equipment such as enterprise servers and switches, workstations, base stations, network attached storage, FPGA testers, network testers, and other test and measurement equipment employ several high-current CPUs, ASICs, FPGAs, and DDR memory – all of which need high power, while the available board area is steadily decreasing. This paper will discuss volumetric co-design methodology and packaging construction trade-offs for 3D SiP power modules and also introduce the straddle mounted inductor assembly technique. Also provided are details around the SiP eco-system, co-design, construction, materials, and circuit topology.
|11:40am-12:05pm||RESCHEDULING ALERT: JOHN PARK'S PRESENTATION HAS BEEN CANCELLED DUE TO ILLNESS.|
THE PRESENTATION FROM DR. DOUGLAS HOPKINS AND TZU-HSUAN CHENG WILL BE PRESENTED DURING THIS TIME SLOT.
SiP Layout and Analysis Design Tool/Flow
This presentation will outline a novel design methodology that overcomes many of today’s challenges for co-designing and co-analyzing multi-chip(let) packages.
Development of WBG Power System-in-Package with Highly Thermally Conductive Organic Laminates
|12:05pm-12:30pm||High Performance Reliability of SiP Module by Mold Encapsulation with EMI Shielding|
System-in-Package (SiP) modules play an important role in making IoT smart devices, integrating more functions and simplifying final product assembly. To enable multi-function integration in SiP design, several novel SiP technologies have been developed, including enhanced reliability with mold encapsulation and package level EMI shielding (Conformal Shielding (CFS) and Compartmental Shielding (CPS)).
In conventional non-molded SiP module designs, standard component footprint layout, with large volume solder wetting is utilized for both making the electrical connection and providing sufficient adhesion to pass shock, vibration and drop test requirement. By applying a mold encapsulation process in the SiP module design, the mold compound provides protection for components inside SiP module that allow designer to shrink component footprint to smaller size and achieve higher density component placement. However, the high density of electrical functions may result in electromagnetic noise interference (EMI) on nearby components and a high level of total radiated EMI from the system product. To resolve this an advanced conformal shielding (CFS) and compartmental shielding (CPS) process has been developed. The conformal shielding reduces EMI on molded SiP modules by depositing a sputtered thin metal layer on the module’s top and side surfaces. The compartmental shielding process enables the definition of shielded compartments through a conductive barrier inside the package. This provides a method for reducing the product design area requirement as well as near field EMI from component to component. In addition, a double sided molding capability has been developed to provide further improvements in size reduction and thermal dissipation as well as electrical performance through shorter electrical paths via vertical connection structures between the active chip and related components.
This talk will explore these items above and share key considerations for IoT smart device SiP modules where integration and performance are increasingly important.
Live programming is paused for attendee lunch break on own.
|1:15pm-1:40pm||Packaging Materials enabling SIP Designs|
To realize System in Package device designs, having high performance dielectric laminate materials with metallizations that can be patterned and processed is paramount to the heterogenous integration schemes required achieve the envisioned use cases. DuPont offers several product lines from build up films and plating solutions to low temperature co-fired ceramic (LTCC) and thick film metallization pastes which contribute specific functionality for different scenarios of packaging.
LTCC (Low Temperature Co-fired Ceramic) is well suited for long life and harsh environment mmWave use cases such as 5G base stations. High degrees of heterogenous integration are enabled in LTCC due to very stable, high performance materials such as high thermal conductivity, low thermal expansion ceramic dielectrics that are cofired with high conductivity noble metals such as silver and/or gold to make hermetic, high reliability systems in package (SiP and AiP) with mmWave performance (Dk ~7, Df < 0.0015). Ultra-Low Loss Dielectrics such as our CYCLOTENE™ products are well suited for high frequency applications due to low moisture absorption, low dielectric constant and low dielectric loss. These materials have been used for many years in fabrication of active and passive RF devices including integrated passive devices (IPDs). Future material development is focused on improving the performance of these materials while reducing their cure temperature. (Dk ~2.6, Df<0.002). Flexible materials such as our Pyralux® and Kapton® products have a proud legacy of performance and reliability. Flexible dielectric substrate materials have brought advanced electronic circuits into products ranging from smartphones to medical devices. The ability of flex circuits to accommodate tight bending radii and eliminate the need for cables and connectors gives designers greater flexibility and enables products that would not otherwise be possible.
The webinar will present not only how the currently available materials have attractive material properties, but also how the material platforms can be utilized in test vehicles and device builds to meet performance specifications in way that is aligned with established high-volume assembly operations.
General Chair: Mark Gerber, ASE Group