Live Virtual Workshop on Advanced System-in-Pack


IMAPS Live Virtual Workshop on


Wednesday, November 18, 2020 | 11:00am-2:15pm EASTERN | MS Teams

This workshop has been recorded. The recording and presentation files have been archived for workshop attendees only. Contact for more information!

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Event Description:
Power, Performance and expanded functionality are all driving factors in considering a higher level integrated device solutions.  Today, more and more companies are looking for ways to differentiate themselves by providing more integrated silicon solutions but with the flexibility of integrating different silicon nodes, and other complementary devices.  This workshop will allow some leading industry experts to talk about several key contributors to enabling more integrated solutions through design, materials and packaging.  IMAPS is excited to provide this focused workshop as a pre-cursor to the 2021 Advanced SiP Conference being planned for next year.  We look forward to your participation.

Workshop Program (Subject to Change):

11:00am-11:15amOpening Remarks

General Chair: Mark Gerber, ASE Group
11:15am-11:40amIncrease Power Density and Simplify Designs Using 3-D SiP Modules
Today, designers are demanding an overall form-factor reduction to save board space, increase functionality, and allocate more circuit board real estate toward end-user applications – all with less space allocated to power management where not just the X-Y shrink but the 3D volumetric shrink is required. For example, in today’s Telecommunications Cloud Infrastructure systems, board space and power density are challenging particularly in power supply designs where several high-current point-of- load rails are present. End equipment such as enterprise servers and switches, workstations, base stations, network attached storage, FPGA testers, network testers, and other test and measurement equipment employ several high-current CPUs, ASICs, FPGAs, and DDR memory – all of which need high power, while the available board area is steadily decreasing. This paper will discuss volumetric co-design methodology and packaging construction trade-offs for 3D SiP power modules and also introduce the straddle mounted inductor assembly technique. Also provided are details around the SiP eco-system, co-design, construction, materials, and circuit topology.
Steven Kummerl, Senior Member of Technical Staff, Texas Instruments
Steven Kummerl received his B.S. degree in Mechanical Engineering from University of Texas El Paso. He is a senior member of technical staff at Texas Instruments supporting semiconductor packaging and has worked in the field of high volume/high mix surface mount assemblies for more than 13 years and over 10 years at TI supporting advanced packaging R&D.  He holds over 35 patents in the field of package design and has authored multiple publications focused in packaging design, SMT package assembly, & reliability.


SiP Layout and Analysis Design Tool/Flow

This presentation will outline a novel design methodology that overcomes many of today’s challenges for co-designing and co-analyzing multi-chip(let) packages.
John Park, Product Management Director, Cadence Design Systems
John Park brings over 35 years of design and EDA experience to his role as Product Management Director for Advanced Semiconductor Packaging at Cadence Design Systems. In this role, John leads a team responsible for defining cross-domain solutions and methodologies for IC, package & PCB co-design and analysis.

Development of WBG Power System-in-Package with Highly Thermally Conductive Organic Laminates
Douglas Hopkins, Professor, North Carolina State University
Professor Hopkins received his Ph.D. in Electrical Engineering from Virginia Tech, and spent his early career at the R&D centers of GE and Carrier Air-Conditioning Companies in advanced power electronics systems for military and commercial applications. He now directs the Laboratory for Packaging Research in Electronic Energy Systems (PREES) at North Carolina State University, has over 190 publications, and is an IMAPS Fellow.
Tzu-Hsuan Cheng, North Carolina State University
Tzu-Hsuan Cheng received his B.S. in Mechanical Engineering from the National Central University, Taoyuan, Taiwan, and M.S. degree from the Department of Power Mechanical Engineering, National Tsing Hua University, Hsinchu, Taiwan, in 2014. He was a Power IC Packaging R&D Engineer in Delta Electronics, Taoyuan, Taiwan, and is currently pursuing a Ph.D. degree in Electrical and Computer Engineering, North Carolina State University.

12:05pm-12:30pmHigh Performance Reliability of SiP Module by Mold Encapsulation with EMI Shielding
System-in-Package (SiP) modules play an important role in making IoT smart devices, integrating more functions and simplifying final product assembly. To enable multi-function integration in SiP design, several novel SiP technologies have been developed, including enhanced reliability with mold encapsulation and package level EMI shielding (Conformal Shielding (CFS) and Compartmental Shielding (CPS)).
In conventional non-molded SiP module designs, standard component footprint layout, with large volume solder wetting is utilized for both making the electrical connection and providing sufficient adhesion to pass shock, vibration and drop test requirement. By applying a mold encapsulation process in the SiP module design, the mold compound provides protection for components inside SiP module that allow designer to shrink component footprint to smaller size and achieve higher density component placement. However, the high density of electrical functions may result in electromagnetic noise interference (EMI) on nearby components and a high level of total radiated EMI from the system product. To resolve this an advanced conformal shielding (CFS) and compartmental shielding (CPS) process has been developed. The conformal shielding reduces EMI on molded SiP modules by depositing a sputtered thin metal layer on the module’s top and side surfaces. The compartmental shielding process enables the definition of shielded compartments through a conductive barrier inside the package. This provides a method for reducing the product design area requirement as well as near field EMI from component to component. In addition, a double sided molding capability has been developed to provide further improvements in size reduction and thermal dissipation as well as electrical performance through shorter electrical paths via vertical connection structures between the active chip and related components.
This talk will explore these items above and share key considerations for IoT smart device SiP modules where integration and performance are increasingly important.
Vincent (Kuo-Hsien) Liao, ASE Group
Vincent Liao (Kuo-Hsien Liao) received his M.S. degree in electrical engineering from the National Chung Hsing University in Taiwan in 2012. He has more than 15 years’ experience in wireless system in package (SiP) design and product engineering in ASE and holds more than 30 patents.

12:30pm-12:50pmLunch Break
Live programming is paused for attendee lunch break on own.
Recent Advancements in System-in-Package (SiP) Technologies
System-in-Package (SiP) technologies continue occupying the center stage of semiconductor-packaging theater, frequently highlighted by fanfares of novel engineering implementations tailored to 5G, High-Performance Computing (HPC), Automotive, etc.  In this talk, we will review recent advancements in SiP, with a focus on three selected topics: Double-Sided Molding Considerations, E.M.I. Shielding Considerations, and Laser-Assisted Bonding Considerations.
Michael Liu, Head of Global Technical Marketing, JCET Group
Michael M. Liu is Head of Global Technical Marketing at JCET Group Co., Ltd., where he oversees the company’s corporate strategy development and technical marketing activities.  Michael Liu has 17 years of industry experience within the realm of RF Microelectronics, Analog and Mixed-Signal Semiconductors.  Michael attended Oregon State University, UCLA, and Stanford University and presently lives in Orange County, CA, with his wife and three children

1:15pm-1:40pmPackaging Materials enabling SIP Designs
To realize System in Package device designs, having high performance dielectric laminate materials with metallizations that can be patterned and processed is paramount to the heterogenous integration schemes required achieve the envisioned use cases.  DuPont offers several product lines from build up films and plating solutions to low temperature co-fired ceramic (LTCC) and thick film metallization pastes which contribute specific functionality for different scenarios of packaging. 
LTCC (Low Temperature Co-fired Ceramic) is well suited for long life and harsh environment mmWave use cases such as 5G base stations.  High degrees of heterogenous integration are enabled in LTCC due to very stable, high performance materials such as high thermal conductivity, low thermal expansion ceramic dielectrics that are cofired with high conductivity noble metals such as silver and/or gold to make hermetic, high reliability systems in package (SiP and AiP) with mmWave performance (Dk ~7, Df < 0.0015).  Ultra-Low Loss Dielectrics such as our CYCLOTENE™ products are well suited for high frequency applications due to low moisture absorption, low dielectric constant and low dielectric loss.  These materials have been used for many years in fabrication of active and passive RF devices including integrated passive devices (IPDs).  Future material development is focused on improving the performance of these materials while reducing their cure temperature. (Dk ~2.6, Df<0.002).  Flexible materials such as our Pyralux® and Kapton® products have a proud legacy of performance and reliability. Flexible dielectric substrate materials have brought advanced electronic circuits into products ranging from smartphones to medical devices. The ability of flex circuits to accommodate tight bending radii and eliminate the need for cables and connectors gives designers greater flexibility and enables products that would not otherwise be possible. 
The webinar will present not only how the currently available materials have attractive material properties, but also how the material platforms can be utilized in test vehicles and device builds to meet performance specifications in way that is aligned with established high-volume assembly operations.
Brian Laughlin, Principal Scientist, DuPont
Brian Laughlin, Ph.D. is a materials scientist and ceramist with 14 years of experience with DuPont Micro Circuit Materials (MCM).  During his career, he has researched glass chemistry, ceramic formulations, and thick film Ag paste and their use in numerous electronic devices.  Since 2017, Dr. Laughlin is the principal scientist acting as the DuPont MCM technology leader scouting the intersections between the DuPont material offerings and the devices required for the 5G telecommunications buildout.

1:40pm-1:50pmClosing Remarks

General Chair: Mark Gerber, ASE Group