Device Packaging PDCs


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What are PDCs?

Professional Development Courses are supplemental two-hour classroom-style tutorials with a narrow educational focus taught by the best in the industry. The topics offered at DPC 2023 are designed to help attendees broaden their scope of knowledge.

Device Packaging 2023 PDC Course Offerings

Attendees must register for each course as an add-on to their overall symposium registration at $325 each for early registration or $425 after February 1. Attendees may select up to one course in each time slot. 

Make sure to review your preferred course's date and time slot before registration. Course fees are non-refundable.  


Course Fees and Inclusions

Course Fees: $325 per course before February 1/$425 per course February 1 and after.

Fees include access to the 2-hour course led by reputable industry leaders.
These fees are non-refundable but may be transferred to another registrant prior to the start of the course. No transfers will be accepted once the course has begun. 

How to Register

  1. Click here to get started.
  2. Log into your member account or create a guest* account.
    *Remember! Member, Nonmember, Speaker, Chair, and Student event registrations include a one-year IMAPS membership. Make sure to populate your account thoroughly. Guest accounts will be converted to member accounts within 30 days of your event registration.
  3. Select your overall conference registration type (Member, Nonmember, Speaker, Chair, Student).
    Only planning to attend a PDC? Select "PDC Only" as your registration type. PDC-only registrants will not have access to additional conference content. 
  4. Choose your course(s) selection in the time slot drop-down boxes. Select up to one course per time slot.
  5. Check out. You will receive a confirmation email detailing your registration. 

If you need to add or change course selection(s) after completing a registration, please contact IMAPS 

Course Descriptions

The Evolution of Flip Chip Package Technology
Mark Gerber, ASE US, Inc.

This PDC course will provide a historical overview and background on the evolution of flip chip packaging as well as short market perspective on this platform. Mobile, Infrastructure, Automotive, High Reliability, Medical and High-Performance Network and Computing all rely on Flip Chip technology to enable their silicon solutions. Although the use of new technologies such as Fan-Out hold promise for certain applications, flip chip advancements continue to challenge many new technology competitors from a price and reliability perspective and may end up driving hybrid approaches. Interconnect structure, process flows, materials and package integration process methods for evolving Flip Chip applications will be discussed in detail. Understanding the trade-offs between the different bump structures and package platforms is key in determining the silicon device layout and the type of design rules that can be leveraged for new products. As part of this course, the assembly process details will be discussed and will include Mass Reflow, Thermo-Compression Non-Conductive Paste (TCNCP) bonding, Laser Assisted Bonding, and Hybrid Bonding. Reliability aspects such as IMC formations and ways to address will also be covered as a key consideration for Interconnect decisions.

Packaging Processes, Materials, Quality and Reliabiity

Syed Sajid Ahmad, Consultant

The course presents manufacturing, materials, quality and reliability info in terms understandable to engineering and non-engineering personnel. Packaging characteristics and drivers will be outlined. Types of packages and critical differences among them and their applications will be discussed. The course will look at the design selection to meet use and application environments. Step-by step manufacturing flow for plastic packages will be presented as an example to understand the complexity of processes, materials and equipment involved in their manufacture. Advanced packaging will be introduced. Materials selection with respect to application environments will be discussed. Quality and reliability issues related to chip packaging and assembly and their solution will be outlined.

Chiplet Design and Heterogeneous Integration Packaging 
John Lau, Unimicron

Chiplet is a chip design method and heterogeneous integration (HI) is a chip packaging method. HI uses packaging technology to integrate dissimilar chips, photonic devices, and/or components (either side-by-side, stacked, or both) with different sizes and functions, and from different fabless design houses, foundries, wafer sizes, feature sizes and companies into a system or subsystem on a common package substrate. For the next few years, we will see more implementations of a higher level of chiplet designs and HI packaging, whether it is for time-to-market, performance, form factor, power consumption or cost. In this lecture, the introduction, recent advances, and trends in chiplet design and HI packaging will be presented. The contents are: (1) Introduction; (2) System-on-Chip (SoC); (3) Chiplet Design and HI Packaging; (4) Advantages and Disadvantages of Chiplet Design and HI Packaging; (5) AMD Chiplet Design and HI Packaging: (a) EPYZ and (b) RYZEN; (6) Intel Chiplet Design and HI Packaging: (a) FOVEROS, (b) FOVEROS Direct, and (c) Ponte Vecchio; (7) TSMC chiplet Design and HI Packaging: (a) SoIC, (b) SoIC + CoWoS, and (c) SoIC + InFO PoP; (8) Chiplets Lateral Interconnects (Bridges): (a) Intel’s EMIB, (b) IBM’s solution for EMIB, (c) Applied Materials’ Bridge Embedded in Fan-Out EMC, (d) SPIL’s FO-EB, (e) TSMC’s LSI, (f) ASE’s sFOCoS, (g) IME’s EFI, (h) Amkor’s S-Connect Fan-Out Interposer, and (i) UCIe; (9) HI Packaging on Organic Substrates: many examples; (10) HI Packaging on Silicon Substrates (TSV-Interposers): many examples: (a) Leti, (b) IME, (c) HKUST, (d) ITRI, (e) Xilinx/TSMC, (f) Altera/TSMC, (g) NVidia/TSMC, (h) AMD/UMC, (i) AMD’s Active Interposer, (j) Intel’s FOVEROS, (k) TSMC’s SoIC, and (l) Samsung’s X-Cube; (11) HI Packaging on Silicon Substrates (TSV-Less Interposers) such as Bridges; (12) HI Packaging on Ceramic Substrate: one example; (13) HI Packaging on Fan-Out RDL (Organic Interposers) for High Performance Applications: many examples: (a) STATSChipPac’s FOFC-eWLB, (b) ASE’s FOCoS, (c) MediaTek’s FO-RDLs, (d) TSMC’s InFO_oS and InFO_MS, (e) Samsung’s Si-Less RDL Interposer, (f) TSMC’s RDL-Interposer, (g) ASE’s FOCoS (Chip-Last), (h) Shinko’s Organic RDL-Interposer, and (i) Unimicron’s Hybrid Substrate; (14) Assembly Technologies for Chiplet Design and HI Packaging: (a) SMT, (b) Solder Bumped Flip Chip, (c) CoW, (d) WoW, (e) TCB, and (f) Bumpless Cu-Cu Hybrid Bonding; and (15) Trends in Chiplet Design and HI Packaging.

Introduction to Fan-Out Wafer Level Packaging (FOWLP)
Beth Keser, IMAPS President

Fan-out wafer level packaging (FO-WLP) technologies have been developed across the industry over the past 15 years and have been in high volume manufacturing for over 10 years. FO-WLP has matured enough that it has come to a crossroads where it has the potential to change the electronic packaging industry by eliminating wirebond and bump interconnections, substrates, leadframes, and the traditional flip chip or wirebond chip attach and underfill assembly technologies across multiple applications. This course will cover the advantages of FO-WLP, potential application spaces; package structures available in the industry; materials, equipment and process challenges; and reliability.

Course outline:

  • Current Challenges in Packaging
  • Definitions and Advantages
  • Applications
  • Package Structures
  • Materials
  • Equipment
  • Design Rules & Reliability   

Wire Bond Process Optimization
Henri Seppaenen, Kulicke & Soffa Industries

This wire bonding professional development course provides deep dive into wire bonding technologies, techniques, process development, and optimization. The course will introduce wire bonding technologies from thin wire ball bonding and large wire wedge bonding to heavy ultrasonic copper ribbon bonding. After the introduction, we present wire bonding fundamentals, the physics of bonding, and material science to understand the bonding process, process optimization, and reliability. We share practical methods for the wire bond process optimization, including parameter selection, destructive and non-destructive testing, and how to use analysis tools such as trace analysis, DOE, and response surface. The course will also highlight the recent advances in wire bonding technology and process development. This course is for anyone who wants to learn or deepen their understanding of wire bonding. Beginners will get practical information on how to improve the bonding process and seasoned professionals will get in-depth science-based knowledge in wire bonding, including references and links to the source materials.

5G/6G/mmWave Materials, Test and Packaging Development Requirements
Urmi Ray, iNEMI

Millimeter-wave (mmWave) frequencies unlock the true potential of 5G. The ultra-wide bandwidths enable faster wireless connection speeds and high capacity with low latency, providing the ideal solution to meet increasing industry and government demands. Many mobile network operators started deploying commercial 5G mmWave networks in 2020. All have massive mmWave deployment plans on their roadmaps. In response, 5G chipset, device, and base station makers are ramping up their design and manufacturing powers to bring more 5G mmWave services to market. It should be noted that 5G requires a complex new ecosystemThe key to enabling this architecture is packaging and system integration, especially involving an effective antenna structure and RFIC communication in cost-effective, small form-factor packages. As full speed development, demonstration and qualification of mmWave systems have accelerated in this decade, different design and packaging architectures are emerging.

This PDC will cover two major topics: (1) Industry roadmapping activities summarizing the technology needs in materials, material characterization and electrical test and (2) integration and packaging options providing a comprehensive landscape of package development including FOWLP as well as laminate/glass based packaging. The specific requirements of materials and process needs (low dielectric material, copper roughness requirements) will be discussed. Product application spaces ranging from mobile/handheld to network infrastructures and automotive/satellite radars are highlighted. Key aspects and guidelines towards a cost/performance trade-off analysis will be summarized.

Polymers for Wafer Level Packaging
Jeff Gotro, InnoCentrix, LLC

The course has been completely updated to include a detailed discussion of the polymers and polymer-related processing for Fan-Out Wafer Level (FOWLP) packaging as well as Fan-Out Panel Level packaging (FOPLP). The course will provide an overview of the important structure-property-process-performance relationships for polymers used in wafer level packaging. The main learning objectives will be:

1) Gain insights on how polymers are used in Fan Out Packaging, specifically mold compounds and polymer redistribution layers (RDL)

2) Understand the key polymer and processes challenges in Fan Out Wafer Level Packaging

3) Learn about polymers and processes used in Fan Out Panel Level Packaging including new materials for mold compounds and a detailed description of the polymers used for RDL in FOPLP.

Course Topics:

  •  Overview of polymers used in Wafer Level Packaging
  •  Wafer level process flows (chip first versus chip last (RDL first))
  •  Epoxy Mold compounds for eWLP
  •  Photosensitive polyimides and polybenzoxazoles
  •  Polymer reliability challenges in Fan-out wafer level packaging
  •  Processes and materials for Fan Out Panel Level Packaging
  •  Wafer versus panel processing; polymer challenges and solutions

Failure Analysis in Semiconductor Package Assembly 
Tom Dory, Fujifilm Electronic Materials USA

The objective of this PDC is to provide the participants with an overview of the technologies, materials, and processes involved in the latest assembly failure analysis methods.

PDC participants will receive a detailed review of failure analysis methods and reliability testing in assembly. Quickly finding and eliminating package defects and failures due to assembly issues is critical. Package reliability directly affects manufacturing yield, time to market, product performance, customer satisfaction and cost. Many process steps and controls are needed for a high yield and reliable assembly process. A thorough understanding of product and technology reliability principles and mechanisms of failure is essential. Knowledge of defects and failure mechanisms enables a high yielding successful assembly process through material choices, package design, process optimization, and thermo-mechanical considerations. Fault isolation, failure analysis, and materials analysis play a major role in the improvement of yield and reliability. Coordination of engineers from many disciplines is needed in order to achieve high yield and reliability. Each engineer needs to understand the impact of their choices and methods on the final product. This workshop will discuss, using examples, mechanical and thermal failure mechanisms in assembly and detection methods.  

System-in-Package (SiP) - System Solutions Through Miniaturization 
Mark Gerber, ASE US, Inc.

This PDC course will introduce the package platform SiP (System-in-Package) and how some companies are diversifying from SOC (System-on-a-Chip) to leverage heterogeneous silicon integration and package miniaturization to enable system level solutions. A short market perspective will be reviewed as well as how industry segments are leveraging SiP and how the OEM market is evolving and creating system level ecosystems to enabling content revenue- a key area of IOT. SiP general process flow details will be covered as well as key process considerations for yield improvements. In addition, a brief overview of some of the tools that may be leveraged to help miniaturize module solutions and improve performance. This class will also introduce several variations of the SIP platform using Fan-Out Wafer Level packaging and new embedded substrate technologies are also emerging as powerful future platforms to enable lower power and higher performance devices using solderless interconnects.

Fan Out for Advanced Packaging Applications
John Hunt, TechSearch International

Fan Out technology has evolved as alternative packaging to meet both the need for miniaturization of electronics, using low density Fan Out, and for the complex interconnectivity of complex packages using more advanced Fan Out assemblies.

The increased use of Mobile and IOT for communication and entertainment has driven the need for increased capability of data centers. Fan Out technology is currently used for many of these applications. It has enabled the heterogeneous integration of die and memory with improved electrical performance and lower cost than traditional 2.5 packaging for data center requirements.

We will review how wafer level processing technologies, the evolution of substrate technologies, and Flip Chip packaging have combined to enable advances in Fan Out packaging. These structures are used for a variety of automotive, IoT, advanced mobile, server and AI applications. They allow for higher levels of integration and sophistication than has been possible in the past with traditional packaging techniques.

A brief overview of the concept of Fan Out packaging, the history of its evolution, followed by more detailed discussions of recent Fan Out developments for advanced applications, including the integration of chiplets into complex packages is included in this course.

Thermal Challenges and Opportunities of Advanced Packages and Microelectronics Systems
Victor Chiriac, Global Cooling Technology Group

The digital world requires higher performance, more data and faster processors. Heterogeneous Computing involves innovative packaging solutions for the central processing units (CPUs), the graphics processing units (GPUs), high speed interconnects and other elements that enable superior computing. The emergence of 5G/6G leads to significant rise in mobile communication, IoT technology and beyond, providing the infrastructure needed to carry huge amounts of data, allowing for a smarter and more connected world. This course will highlight the current and future thermal challenges and opportunities spanning from the package to the system level, impacting the small to large electronics and other advanced systems of the future.

Semiconductors in Automotive - Technology Trends and Reliability
Vikas Gupta, ASE US, Inc. & Pradeep Lall, Auburn University

The first part of the PDC will provide a summary of key disruptive trends in automotive electronics in the upcoming years. The increased emphasis on autonomous driving as well as electrification of vehicles has resulted in enormous changes for semiconductors and packaging. Following megatrends will be discussed

  • Autonomous
    • Introduction of advanced nodes and packages for processors
    • Sensing technologies
  • Electrification
    • Power systems trend
    • Wide band gap implementation

In the second part of this professional development course, the design, materials, and reliability strategies for automotive electronics will be presented. Electronics are increasingly being used in automotive platforms for a variety of mission-critical and safety-critical activities, such as guidance, navigation, control, charging, sensing, and operator interaction. Over the last two decades, automotive platforms have expanded to incorporate hybrid and fully-electric vehicles. Much of the electronics is located under the car’s hood or in the trunk, where temperatures and vibration levels are far higher than in consumer office applications. During the vehicle’s use-life, electronics in the automotive underhood may be exposed to sustained high temperatures of 125-150C for extended periods of time. The automotive electronics council (AEC) has graded electronics for automotive purposes into four categories: grade-0, grade-1, grade-2, and grade-3. Grade-0 components have the most demanding criteria of the four grade categories, with predicted power temperature cycling ranging from -40C to +150C for 1000 cycles and ambient temperature cycling ranging from -55C to +150C for 2000 cycles. Furthermore, the grade-0 components are expected to be capable of sustaining high-temperature storage for 1000 hours at 175C. With the introduction of new packaging architectures, the area of packaging applications has continued to evolve, allowing for powerful computing on mobile automobile platforms. New materials and integration technologies have also emerged, allowing for tighter integration of electronics sensing and processing into the structural characteristics of the vehicle. The automobile platform faces a series of constraints particular to the real-time context for enabling sophisticated functionality.