Device Packaging PDCs

   

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PROFESSIONAL DEVELOPMENT COURSES

   

What are PDCs?

Professional Development Courses are supplemental two-hour classroom-style tutorials with a narrow educational focus taught by the best in the industry. The topics offered at DPC 2022 are designed to help attendees broaden their scope of knowledge.

Course Fees and Inclusions

Course Fees: $325 per course before January 27/$425 per course January 27 and after.

Fees include access to the 2-hour course led by reputable industry leaders.
These fees are non-refundable but may be transferred to another registrant prior to the start of the course. No transfers will be accepted once the course has begun. 

How to Register

  1. Click here to get started.
  2. Log into your member account or create a guest* account.
    *Remember! Member, Nonmember, Speaker, Chair, and Student event registrations include a one-year IMAPS membership. Make sure to populate your account thoroughly. Guest accounts will be converted to member accounts within 30 days of your event registration.
  3. Select your overall conference registration type (Member, Nonmember, Speaker, Chair, Student).
    Only planning to attend a PDC? Select "PDC Only" as your registration type. PDC-only registrants will not have access to additional conference content. 
  4. Choose your course(s) selection in the time slot drop-down boxes. Select up to one course per time slot.
  5. Check out. You will receive a confirmation email detailing your registration. 

If you need to add or change course selection(s) after completing a registration, please contact IMAPS info@imaps.org. 

Course Descriptions

PDC1: 
Introduction to Fan-Out Wafer Level Packaging

Beth Keser, Intel Corp.

Fan-out wafer level packaging (FO-WLP) technologies have been developed across the industry over the past 15 years and have been in high volume manufacturing for over 10 years. FO-WLP has matured enough that it has come to a crossroads where it has the potential to change the electronic packaging industry by eliminating wirebond and bump interconnections, substrates, leadframes, and the traditional flip chip or wirebond chip attach and underfill assembly technologies across multiple applications. This course will cover the advantages of FO-WLP, potential application spaces, package structures available in the industry, design rule roadmap, reliability, and cost. 
 
Course outline: 

  • Current Challenges in Packaging, 
  • Definitions and Advantages, 
  • Applications, 
  • Package Structures, 
  • Design Rules, 
  • Reliability, 
  • Cost 

Who Should Attend: 
Engineers and managers responsible for advanced packaging development, package characterization, package quality, package reliability and package design should attend this course. Suppliers who are interested into supporting the materials and equipment supply chain should also attend. Both newcomers and experienced practitioners are welcome.

PDC2: 
The Evolution of Flip Chip Package Technology
Mark Gerber, ASE US, Inc.

This PDC course will provide a historical overview and background on the evolution of flip chip packaging as well as short market perspective on this platform. Mobile, Infrastructure, Automotive, High Reliability, Medical and High-Performance Network and Computing all rely on Flip Chip technology to enable their silicon solutions.  Although the use of new technologies such as Fan-Out hold promise for certain applications, flip chip advancements continue to challenge many new technology competitors from a price and reliability perspective and may end up driving hybrid approaches.  Interconnect structure, process flows, materials and package integration process methods for evolving Flip Chip applications will be discussed in detail. Understanding the trade-offs between the different bump structures and package platforms is key in determining the silicon device layout and the type of design rules that can be leveraged for new products. As part of this course, the assembly process details will be discussed and will include Mass Reflow, Thermo-Compression Non-Conductive Paste (TCNCP) bonding and Laser Assisted Bonding. Reliability aspects such as IMC formations and ways to address will also be covered as a key consideration for Interconnect decisions.

PDC3: 
Failure Analysis in Semiconductor Package Assembly 
Tom Dory, Fujifilm Electronic Materials USA

This PDC provides details on current failure analysis methods and reliability testing in package assembly. 
PDC participants will receive a detailed review of failure analysis methods and reliability testing in assembly. Quickly finding and eliminating package defects and failures due to assembly issues is critical. Package reliability directly affects manufacturing yield, time to market, product performance, customer satisfaction and cost. Many process steps and controls are needed for a high yield and reliable assembly process. A thorough understanding of product and technology reliability principles and mechanisms of failure is essential. Knowledge of defects and failure mechanisms enables a high yielding successful assembly process through material choices, package design, process optimization, and thermo-mechanical considerations. Fault isolation, failure analysis, and materials analysis play a major role in the improvement of yield and reliability. Coordination of engineers from many disciplines is needed in order to achieve high yield and reliability. Each engineer needs to understand the impact of their choices and methods on the final product. This workshop will discuss, using examples, mechanical and thermal failure mechanisms in assembly and detection methods.  
The objective of this workshop is to provide the participants with an overview of the technologies, materials, and processes involved in the latest assembly failure analysis methods.

PDC4:
5G mmWave Packcage Development Requirements and Solutions 
Urmi Ray, Consultant

The fifth Generation (5G) mobile communication era is expected to address the insatiable need for data communication by introducing mmWave technology and protocols. The unprecedented latencies offered by 5G Networks will enable users to indulge in gigabit speed immersive services regardless of geographical and time dependent factors.
The key to enabling this architecture is packaging and system integration, especially involving an effective antenna structure and RFIC communication in cost-effective, small form-factor packages. As full speed development, demonstration and qualification of mmWave systems have accelerated in 2017, different design and packaging architectures are emerging. 
This PDC will provide a comprehensive landscape of package development options including LTCC, eWLB/FOWLP as well as laminate based packaging. The specific requirements of materials and process needs (low dielectric material, copper roughness requirements) are discussed. Multiple different package structures are presented as case studies to demonstrate comparative performance of eWLB vs laminate packages. Product application spaces ranging from mobile/handheld to network infrastructures and automotive/satellite radars are highlighted. Key aspects and guidelines towards a cost/performance trade-off analysis will be summarized.     

PDC5: 
Chip Packaging Processes and Materials
Syed Sajid Ahmad

The course presents manufacturing, materials, quality and reliability info in terms understandable to engineering and non-engineering personnel. Packaging characteristics and drivers will be outlined. Types of packages and critical differences among them and their applications will be discussed. The course will look at the design selection to meet use and application environments. Step-by step manufacturing flow for plastic packages will be presented as an example to understand the complexity of processes, materials and equipment involved in their manufacture. Advanced packaging will be introduced. Materials selection with respect to application environments will be discussed. Quality and reliability issues related to chip packaging and assembly and their solution will be outlined.      

PDC6:
Flip Chip Tutorial 
Richard McKee, Integra Technologies, LLC

Section 1: Overview 

  • Flip Chip Definition 
  • Benefits 
  • Industries where used 
  • Bumping and RDL 
  • Substrate  
  • Implementations 
  • Test and Qualification Considerations 

Section 2: Assembly & Process 

  • Assembly Considerations 
  • Process Considerations 
  • Process Steps 

Process Steps- VIDEOS: 

  • Fluxing 
  • Placement 
  • Reflow 
    • Flux Cleaning 
    • Capillary Underfill 
  • Cure 
  • Encapsulation or Lid Attach 
    • Putting packages in trays (Reminder that this is often a forgotten step)

PDC7:
Advances in Fan-Out Wafer Level Packaging (FOWLP) 
Beth Keser, Intel Corp.

The fifth Generation (5G) mobile communication era is expected to address the insatiable need for data communication by introducing mmWave technologyFan-out wafer level packaging (FO-WLP) technologies have been developed across the industry over the past 15 years and have been in high volume manufacturing for over 10 years. FO-WLP has matured enough that it has come to a crossroads where it has the potential to change the electronic packaging industry by eliminating wirebond and bump interconnections, substrates, leadframes, and the traditional flip chip or wirebond chip attach and underfill assembly technologies across multiple applications. After scale-up and high-volume manufacture of simple single-chip Fan-Out solutions by companies like Qualcomm and Infineon, now many premier semiconductor companies and OEM's have adopted Advanced Fan-Out structures including Apple, MediaTek, HiSilicon, and Xilinx. These companies are leveraging foundry technologies like InFO offered by TSMC as well as OSAT solutions from ASE, Amkor, SPIL, PTI, DECA, and Nepes. This course will cover the advantages of FO-WLP, potential application spaces, advanced package structures available in the industry, technology roadmaps, and benchmarking. The challenges of moving from 300mm FO-WLP to panel will also be discussed. and protocols. The unprecedented latencies offered by 5G Networks will enable users to indulge in gigabit speed immersive services regardless of geographical and time dependent factors.

The key to enabling this architecture is packaging and system integration, especially involving an effective antenna structure and RFIC communication in cost-effective, small form-factor packages. As full speed development, demonstration and qualification of mmWave systems have accelerated in 2017, different design and packaging architectures are emerging.

This PDC will provide a comprehensive landscape of package development options including LTCC, eWLB/FOWLP as well as laminate based packaging. The specific requirements of materials and process needs (low dielectric material, copper roughness requirements) are discussed. Multiple different package structures are presented as case studies to demonstrate comparative performance of eWLB vs laminate packages. Product application spaces ranging from mobile/handheld to network infrastructures and automotive/satellite radars are highlighted. Key aspects and guidelines towards a cost/performance trade-off analysis will be summarized.

PDC8:
System-in-Package (SiP) - System Solutions Through Miniaturization 
Mark Gerber, ASE US, Inc.

This PDC course will introduce the package platform SiP (System-in-Package) and how some companies are diversifying from SOC (System-on-a-Chip) to leverage heterogeneous silicon integration and package miniaturization to enable system level solutions. A short market perspective will be reviewed as well as how industry segments are leveraging SiP and how the OEM market is evolving and creating system level ecosystems to enabling content revenue- a key area of IOT. SiP general process flow details will be covered as well as key process considerations for yield improvements. In addition, a brief overview of some of the tools that may be leveraged to help miniaturize module solutions and improve performance. This class will also introduce several variations of the SIP platform using Fan-Out Wafer Level packaging and new embedded substrate technologies are also emerging as powerful future platforms to enable lower power and higher performance devices using solderless interconnects.          

PDC9:
3D Package Assembly Processes and Technology 
Tom Dory, Fujifilm Electronic Materials USA

This PDC provides details on current and future assembly 3D packaging processes and technologies. The 3D IC and wafer-level packaging area is forecasted to grow to over $2.5 billion by 2016 driven by mobile devices including phone and tablet computers. Advanced packaging requirements require the evolution of back end manufacturing to become more process control driven. The 3D stacked die TSV packaging has advantages, but only in some market segments. In the cell phone market, stacking chips helps to minimize some of the interconnect issues between the logic and the memory chips. Wire bonding remains a key assembly method for 3D memory packages. This workshop will cover 3D and 2.5D (interposer) designs, 3D assembly flow, known good die, KGD, concerns, 3D package testing issues, supply line logistics, thermal management, logic bump out designs, wafer thinning and handling (thermal & laser debonding and residue removal) and interposers with microfluidics cooling built-in. Multichip package options including SiP, SoP and interposer packages will be discussed. The objective of this workshop is to provide the students with an overview of the technologies, materials, and processes involved in the latest 3D and 2.5D assembly processes.