10:00am-7:00pm Pacific

Professional Development Courses

Only one course can be taken per time slot | Separate registration required | Available for $325 per course before January 27/$425 per course January 27 and after.

10:00am-12:00pm Pacific

PDC1:

Introduction to Fan-Out Wafer Level Packaging

Beth Keser, Intel Corp.

PDC2:

The Evolution of Flip Chip Package Technology

Mark Gerber, ASE US, Inc.

PDC3:

Failure Analysis in Semiconductor Package Assembly

Tom Dory, Fujifilm Electronic Materials USA

1:00pm-3:00pm Pacific

PDC4:

5G mmWave Package Development Requirements and Solutions

Urmi Ray, Consultant

PDC5:

Chip Packaging Processes and Materials

Syed Sajid Ahmad

PDC6:

Flip Chip Tutorial

Richard McKee, Integra Technologies, LLC

3:30pm-5:30pm Pacific

PDC7:

Advances in Fan-Out Wafer Level Packaging (FOWLP)

Beth Keser, Intel Corp.

PDC8:

System-in-Package (SiP) - System Solutions Through Miniaturization

Mark Gerber, ASE US, Inc.

PDC9:

3D Package Assembly Processes and Technology

Tom Dory, Fujifilm Electronic Materials USA

Gold Sponsors:

Silver Sponsors:

8:00am-8:20am

General Chair: Prasad Dhond, Amkor Technolgy

Plenary/Keynote Session Sponsored by:

8:20am-9:05am

KEYNOTE 1

FUTURE OF PACKAGING
Moore's law has been the driving engine for science, technology, manufacturing, hardware, software, systems, and applications, contributing to the prosperity of thousands of individuals and 100s corporations in dozens of countries. As Moore's Law benefits begin to slow down, not for the doubling of transistors but for decreasing transistor speeds and the resulting slower computing performances, it is becoming clear that packaging must play a very critical and strategic role, unlike in the past. Prof. Tummala referrers to it as the next Moore‘s Law. Just like Moore‘s Law has both doubling of transistors and simultaneous cost reduction, from node to node every 18-24 months, Moore‘s Law for systems packaging or interconnections has been doing the same. Interconnections have been driven by computing systems and within computing systems, between logic and memory for the highest bandwidth and power efficiency.

The new era of artificial intelligence, mimicking the human brain with several orders better computer performance, is yet another reason for the next Moore's Law. The human brain is the ultimate systems packaging for the highest performance in the smallest size with the lowest power. Moore's Law for Packaging therefore must duplicate this architecture. The packaging or I/Os has historically evolved from DIPs in the 1970s with 16 IOs, QFP in the 1980s with 64 I/Os, ceramic packages in the 1990s with more than 500 I/Os, laminate packages in excess of 1000, and silicon packages approaching 200,000. Artificial intelligence mimicking the human brain may need several orders of magnitude.

Currently, the best Moore's Law for packaging is with wafer-based silicon packaging. But silicon-based packaging has many limitations at the material, device, circuit, and system levels. This talk describes the future need and potential opportunities to address this need.

Rao Tummala, Georgia Tech - Emeritus Professor
Rao Tummala is a Distinguished and Endowed Chair Professor and Director Emeritus at Georgia Tech in the USA. He is well known as an industrial technologist, technology pioneer, and educator. Prior to joining Georgia Tech in 1993, he was an IBM Fellow and Director of Advanced Packaging Lab (APTL), pioneering such major technologies as the industry‘s first plasma display in the 1970s and the industry's first very large 100-chip package with direct copper and water cooling, very much like today's chiplet .As an educator, Prof. Tummala was instrumental in setting up the largest and most comprehensive Academic Center funded by NSF as the first and only NSF Engineering Research Center in Electronic Systems Packaging at Georgia Tech. Such a center, under his leadership, pioneered an integrated approach to System-On- Package research, education, and global industry collaborations. It involved about 30 academic and full-time research faculty, 200 Ph.D. and MS students, and 50-70 industry and academic collaborators from the US, Europe, Japan, Korea, India, and Taiwan. It educated thousands of packaging engineers in classrooms and hands-on labs, and produced more than 1000 engineers with Ph.D., MS, and BS degrees, supplying to every major electronics company in the US

In addition, he is a distinguished Alumni of the Indian Institute of Science, Bangalore, India, the University of Illinois, and the Distinguished Faculty of Georgia Tech. He is a member of NAE, and a fellow of IEEE, IMAPS, and American Ceramic Society. He was the President of IEEE CPMT and IMAPS Societies. He has been an advisor to many semiconductor and system companies, and universities. For his legacy, life-long contributions, IEEE named him as one -in- generation of technologists and the Father of Modern Packaging, creating a Technical Field Award in his name-- IEEE Rao Tummala Electronics Packaging Award.

9:10am - 9:55am

KEYNOTE 2

ADVANCED PACKAGING: ENABLING MOORE'S LAW'S NEXT FRONTIER THROUGH HETEROGENEOUS INTEGRATION
With chiplet architectures becoming mainstream, and recognized as fundamental to enabling the continued economically viable growth of power efficient computing, advanced packaging technologies and architectures are becoming more critical to enabling Moore‘s Law‘s next frontier through heterogeneous integration. In this tutorial, we will cover the advanced package architectures being enabled by AMD to enable PPAC (power, performance, area and cost) improvements as well as enable heterogeneous architectures. The direct Cu-Cu bonding technology used in AMD‘s 3D VCache architecture will be detailed and compared to industry standard 3D architectures for PPAC benefits. Other technologies that are being enabled to advance high performance computing architectures will also be previewed.

Raja Swaminathan, AMD - Senior Fellow
Dr. Raja Swaminathan is a Senior Fellow at AMD responsible for package architecture and advanced technology strategy and development. He was a package architect at Intel for 13 years, moved to Apple to architect their new silicon package architectures before moving to AMD to drive their industry leading chiplet architecture integration. He received his Bachelors‘ from IIT Madras in 2000, PhD from Carnegie Mellon in 2005. He has over 35 US patents in the field and he is an IEEE Senior Member.

General Chair: Prasad Dhond, Amkor Technology

Tuesday Morning Sessions

Tuesday Afternoon Sessions

Tuesday Evening Panel Discussion

6:30pm-8:00pm

(ROOM 107-108)

Sponsored by:

PANEL DISCUSSION:
So Many High Performance Packages:  Is There a Winner?

Moderator: 
E. Jan Vardaman, President and Founder, TechSearch International, Inc.

Panelists:
Details Soon

New packaging solutions are being adopted to achieve the economic advantages that were previously met with silicon scaling.  Heterogeneous integration, especially chiplets, is pivotal in this new era.  The difficulty is making a package choice from the sea of options.  This panel examines the drivers for different options with proponents of different packages, including Silicon Interposer, Fan-out on Substrate, and Embedded Bridge. Advantages of sided-by-side and 3D configurations will be debated. 

GBC Kenote & Plenary Session

(ROOM 107-108)

Welcome to the Global Business Council (GBC) Keynote & Plenary Session on

US DOMESTIC CAPABILITIES FOR ON-SHORING
OF IC PACKAGING AND ASSEMBLY FOR DoD ACCESS

OPENING COMMENTS:
GBC Chairs:  Tom Goodman, Izinus Technologies; Rich Rice, ASE Group; Lee Smith, Consultant

Wednesday Afternoon Sessions

Poster Session Happy Hour

Outside on Patio Overlooking Desert

6:00pm-7:00pm

POSTER SESSION HAPPY HOUR

Improving Semiconductor Manufacturing Yield with Chip-Level FEA
Tyler Ferris, Ansys (Greg Caswell)

Toward Ultra-Precision Surface: Polishing Performance of Dynaqualdiamond Slurry on the Advanced Optoelectronics Material
Tong Liu, Qualdiamond High Tech Inc (Biz Mohammed, Qian He)

Gold Wire Bonding vs. Coated Silver Wire Bonding
William Crockett, Tanaka USA (Dhiraj Bora, Silitronics)

Robert Dean, Auburn University (Moriah Reed, Auburn University; Ian Small, NASA-MFSC)

Jerry Broz, International Test Solutions, a CMC Materials Company (Bret Humphrey)

Mohammad Atif Faiz Afzal, Schrodinger Inc (Alexander Goldberg, Andrea Browning, Shaun Kwak, Mathew Halls)

Thursday, March 10th

Registration

Continental Breakfast Sponsored by:

8:00am-8:10am

Room 107-108

OPENING COMMENTS

General Chairs: Prasad Dhond, Amkor Technology; Nokibul Islam, JCET Group

Plenary/Keynote Sessions Sponsored by:

8:10am-8:55am

KEYNOTE 3

HYBRID BONDING FOR THE NEXT GENERATION OF HIGH PERFORMANCE DEVICES
The electronics industry continues to pursue optimal performance for the insatiable consumer demand of computation intensive products like GPUs, CPUs and AI accelerators. While the monolithic system on chip approach promises exceptional performance, it is costly. The advanced packaging industry has responded to the challenge with 2.5D and 3D integration solutions that bridge the performance gap with heterogeneous integration. Hybrid bonding combined with chiplet architectures within 2.5D will enable the distribution of function and nodes across a chips within a module, providing a path toward more flexible product introduction and innovation.

The design and manufacturing of chip-to chip-communication is complex and has some technology dependencies. One technology limitation in realizing a monolithic performance with heterogeneous integration is solder interconnect scalability. Hybrid bonding is a revolutionary platform technology that solves the interconnect scalability problem and delivers enhance performance compared to the conventional Cu microbump.

The Direct Bond Interconnect (DBI®), more generally known as hybrid bonding, offers a performance boost that enables novel 3D architectures via disaggregation and chiplet implementation, in spite Moore‘s law slowing. The efficient interconnect between circuit functions at the wafer, die and package level, will fuel semiconductor company roadmaps for decades. The performance advantages, ease of integration of such a hybrid interconnect will be discussed in chip to wafer and chip to chip applications. The key areas of innovation anticipated to proliferate the technology within the entire advanced packaging supply chain will be presented.

Laura Mirkarimi, Xperi Corp. - VP of Engineering, 3D Portfolio and Bonding Technology
Laura Mirkarimi is VP of Engineering, 3D Portfolio and Bonding Technology at Xperi Holding Corporation, San Jose, California. She received a PhD in Materials Science at Northwestern U. Dr. Mirkarimi leads the 3D team at Xperi. Prior to joining Xperi, she developed electronic devices including ferroelectric memory, transparent conductors and photonic crystal resonators at Hewlett Packard Laboratories for 12 years. She holds more than 50 patents and 45 publications.

KEYNOTE 4

INTELLIGENT POWER AND SENSING SOLUTIONS FOR A SUSTAINABLE FUTURE
Vehicle electrification, autonomous driving, renewable energy and big data are enabling unprecedent changes in human life, and are pushing the technology to new limits. Those major evolutions require power electronics and sensing solutions, driven by optimum technology and packaging solutions to deliver maximum product efficiency. This talk will review recent progress in front end technology, packaging (discrete, power modules) and highlight the importance of system integration.

It will illustrate the challenges of simultaneously meeting a wide range of power density, product scalability, cost and reliability requirements, and are made possible by the ongoing progress in semiconductor research, engineering and manufacturing.

Jerome Teysseyre, ON Semiconductor – VP, Head of Package Development and Engineering
Jerome is having 22 years of experience in Package development. He holds a master in material sciences from Grenoble Institute of Technology.

He started his career at STMicroelectronics where he held several positions until 2014. Jerome managed ST‘s package assembly process and technology development group in Europe covering  the broad portfolio of mobile phone applications with BGA, System in Package, embedding, optical camera sensors   and smart power packages. From 2010 to 2014 Jerome lead Asian teams in charge of Wafer level fan in, fan out, Camera and optical sensor development and developed packaging south east Asia center of competency to support the growing automotive market needs. Among his function in Singapore, he developed the Next Generation E-WLB (fan out) in partnership with Statchippac and Infineon. Jerome moved to Fairchild in 2014 (acquired by onsemi in 2016) and shifted his focus to power semiconductor to enable differentiated package portfolio on automotive , industrial power modules and QFN - SIP migration for Cloud computing.

Jerome‘s team are focusing on the extension of automotive package portfolio and solutions for wide band gap.