Device Packaging Agenda


CONFERENCE PROGRAM AGENDA


IMAPS is pleased to present the DEVICE PACKAGING CONFERENCE. Feature presentations, panel discussions, GBC and PDCs are listed below! 


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Monday, March 13th


Professional Development Courses

Only one course can be taken per time slot | Separate registration required | Available for $325 per course before February 1/$425 per course February 1 and after.

10:00am-10:30am 

COFFEE BREAK IN FOYER

12:30pm-1:00pm 

LUNCH    (boxed lunches can be picked up in the foyer from 12:30pm-1:00pm)
Only provided for those attendees registered for BOTH Morning and Afternoon PDCs

3:00pm-3:30pm 

COFFEE BREAK IN FOYER 

5:30pm-7:00pm

WELCOME RECEPTION
Followed by the DEI Roundtable 
**NEW at DPC this Year**

(All Attendees are invited to attend)
Thank you to our 2023 Premier Sponsors!
Platinum Sponsor:


Gold Sponsors:



Silver Sponsors:

Silver Sponsor - Cadence

Sponsor: Adeia



7:00pm-8:00pm

IMAPS/3D InCites DEI Roundtable Discussion on:
DEI: It Takes a Village

7:00 pm – 8:00 pm

DEI Chair: 
Robin Davis, Deca Technologies

Moderator & Podcaster: 
Françoise von Trapp, 3D InCites


Panelists: 
Francesca Domingo, EMD Group | Head of University Relations & Talent Strategy, EMD Group 
Lalitha Immaneni, Intel Corp. | VP Architecture Design and Technology Solutions
Rebeca Obregon-Jimenez, Avnet | SVP Strategic Business Engagements & Supplier Management
Robin Stubenhofer, Kansas City National Security Campus (KCNSC) managed by Honeywell | VP of Engineering


The target audience is not HR or hiring managers, but the regular attendees who may be wondering what they can do to help create an atmosphere of equity and inclusion at their work place. We want to ask the hard questions that people who aren’t impacted by DEI issues might be asking: Why should I care? Why do I need to use my pronouns? What can I do/say to have an impact on our company culture? 

Tuesday, March 14th

7:00am-7:00pm

Registration

7:00am-8:00am

Continental Breakfast Sponsored by:


8:00am-8:20am


OPENING COMMENTS

General Chair: Nokibul Islam, JCET Group

Plenary/Keynote Session Sponsored by:


8:20am-9:05am

KEYNOTE 1

CHALLENGES FOR THE NEXT GENERATION OF PACKAGE TECHNOLOGY AND INTEGRATION

Ahmer Syed, Qualcomm Technologies, Inc.

With Moore’s law slowing down, advanced packaging solutions are required to optimize cost-performance matrix. There is a greater need now than ever before for look at alternate packaging solutions. The task is especially challenging for mobile application where package size and thickness still puts significant constraints on technology options. Similarly, system design and integration continue to put barriers for innovation in a non-vertically integrated supply chain business model.

This presentation highlights these challenges and discusses some of the ways to overcome these with packaging playing a critical and central role.   

Ahmer Syed is a VP of Engineering at Qualcomm in Global Manufacturing Technology and Operations organization. He leads a global team responsible for packaging technology development, NPI, HVM deployment for 5G, mobile, IoT, Connectivity, Automotive, and Compute markets.

A 30+ years veteran of Semiconductor and electronics industry, Ahmer has extensive experience in developing advanced packaging technologies such as Flip Chip, WLCSP, FO-WLP, Package on Package (PoP), QFN, MEMS packaging and System in Package (SiP). He has authored and contributed to more than 70 technical papers and articles on advanced packaging and reliability and has been a keynote speaker in various international conferences. 


9:10am - 9:55am


KEYNOTE 2

ADVANCED PACKAGE SOLUTIONS IN AI/ML AND DATA ERA

High-performance chip size continues to increase up to one reticle size and the cost of the leading-edge silicon node is soaring. Ongoing increase in performance requirements from Cloud to Edge to on-premise use cases require tighter coupling of compute, memory and storage resources. And higher bandwidth and density solution is important for high-end system. So memory coherency and low latency attributes across converged compute infrastructures with interconnect technologies including UCIe (Universal Chiplet Interconnect Express). In this paper, advanced package solutions (FOPKG , 2.xD, 3D, 3.5D) are to be introduced and discussed in terms of challenges and opportunities for emerging high-end computing, memory and mobile platforms.

Seungwook "Stewart" Yoon, Samsung Electronics Dr. YOON is currently working as Corporate VP/Head of Team of Package Solution Planning and Strategy, Samsung Electronics. 
Prior to joining Samsung, He was director of group technology strategy, STATS ChipPAC, JCET Group. He also worked deputy lab director of MMC (Microsystem, Module and Components) lab, IME (Institute of Microelectronics), A*STAR, Singapore. YOON received Ph.D degree in Materials Science and Engineering from KAIST, Korea. He also holds MBA degree from Nanyang Business School, Singapore. He has over 300 journal papers, conference papers and trade journal papers, and over 20 US patents on microelectronic materials and electronic packaging. Served as technical committee member of various international packaging technology conferences, EPTC, ESTC, iMAPS, IWLPC and SEMI.

9:55am-10:15am
CONFERENCE LEADERSHIP RECOGNITION
& 3D InCites Awards

General Chair: Nokibul Islam, JCET Group
Awards: Francoise von Trapp, 3D InCites

10:00am-6:30pm
EXHIBITION OPEN

(Wasaja Ballroom)

10:15am-10:45am
Break in the Exhibit Hall Sponsored by:

Tuesday Morning Sessions

  

HETEROGENEOUS

2D & 3D INTEGRATION Track

FAN-OUT, WAFER LEVEL PACKAGING
& FLIP CHIP Track

NEXT GEN APPLICATIONS Track


TA1: 2D/3D  APPLICATION & TEST
Chairs: Arsalan Alam, AMD; 
Rafi Islam, Cactus Materials
TA2: DESIGN & TECHNOLOGY
Chairs: Robin Davis, Deca Technologies; 
Jiraporn Seangatith, Intel Corp. 

TA3: iNEMI INVITED SESSION:
5G/6G ROADMAP CREATION AND PACKAGING CHALLENGES

Chair: Urmi Ray, iNEMI

10:45am-11:15am

Scaling Interconnect Densities to Meet the Growing Demand for Chiplet Integration
Robin Davis, Deca Technologies (Tim Olson)

Cost Analysis of Fan-out Processes for Chiplet Packaging
Amy Lujan, SavanSys Solutions LLC    
5G/6G MAESTRO Roadmap
Urmi Ray, iNEMI
11:15am-11:45amHeterogenous Integration: Simplifying the Landscape
Michael Kelly, Amkor Technology, Inc. (Dave Hiner, George Scott)
Understanding Warpage Behaviour on Different Handling Platforms of FOWLP                 
Debbie-Claire Sanchez, ERS electronic GmbH
Benchmarking 6G Hardware System Design Needs
Markondeyaraj Pulugurtha, Florida International University
11:45am-12:15pmThe Evolution of Moore’s Law through Chipletized Architectures
Tony Trinh, Mercury Systems (Tom Smelker)

Thin and Ultra-thin Sidewall Protected P-WLCSP
Doug Hackler, American Semiconductor (Ed Prack, MASIP LLC)

5G/6G MAESTRO Materials: Glass Substrates for mmWave/sub-THz Applications
Paul Ballentine, Mosaic Microsystems (Shelby Nelson)
12:15pm-12:45pmAdvanced Test Technologies for Heterogeneous and 2.5D/3D Packaging   
Sunil Banwari, Advantest Inc (Marc Hutner, ProteanTecs)

Using M-Series with Adaptive Patterning to shrink PCB systems into System-In-Packages
Justin Locke, Siemens EDA (Robin Davis, Deca Technologies)

5G Electronics: Bridging the Measurement Challenges
Lucas Enright, NIST


12:45pm-2:00pm

Lunch Break in Exhibit Hall Sponsored by:


Tuesday Afternoon Sessions

  

HETEROGENEOUS 2D & 3D INTEGRATION Track

FAN-OUT, WAFER LEVEL PACKAGING
& FLIP CHIP Track

NEXT GEN APPLICATIONS Track


TP1: PROCESS DEVELOPMENT
Chairs: Suresh Jayaraman, Amkor Technology; Keith Best, Onto Innovation
TP2: WLP & FLIP CHIP: PROCESS & MATERIALS
Chairs: Jobert van Eisden, KMS/Atotech; Tim Smith, Nuvotronics
TP3: PRINTED ELECTRONICS - TBD
Chairs: Robert Dean, Auburn University; Eric MacDonald, University of Texas, El Paso
2:00pm-2:30pmD2W Hybrid Bonding using high accuracy carrier solutions for 3D System Integration
Thomas Uhrmann, EV Group (Jürgen Burggraf, Mariana Pires, EV Group; Chun Ho Fan, Hoi Ping Ng, Ming Li, ASMPT)
TIM Materials – Integration and Assembly Aspects in SIP Applications
Kevin Brenner, Southern Methodist University

Fine-Feature Additively Dry Printed Passive Wireless Sensor Tag
Zabihollah Ahmadi, Auburn University (Masoud Mahjouri-Samani, Robert Dean)

2:30pm-3:00pmAssembly Solutions for Cost-Effective Heterogeneous Integration with Disparate Die Types
Glenn Farris, Universal Instruments Corp.
Liquid Metal Embedded Elastomers as High-performance S-TIM Replacements
Keyton Feller, Arieca (Vivek Singh,  Toby Mea, Allyssa Kerr, Jeffrey Gelorme, Navid Kazem, Arieca)
Development of Electronic Packages with Integrated Environmental Mitigation
Carl Rudd, EngeniusMicro (Peter Zoladz, Greg Poole, Brian English)
3:00pm-3:30pmMicro-Transfer Printing for Efficient 3DHI of 100-300mm Wafers and Glass Panels
Bob Conner, X-Celeprint (Bill Batchelor, David Gomez)
Novel Low Df Thermosetting Film and Photo Imageable Film
Meiten Koh, Taiyo Ink MFG. Co., Ltd    
4D mmW/5G Metasurfaces and Wireless Sensors combining additive manufacturing, morphing and ML technologies
Manos Tentzeris, Georgia Institute of Technology
3:30pm-4:00pm

Break in Exhibit Hall Sponsored by:


4:00pm-4:30pmSolving modern-day challenges in WLP and heterogenous integration through advanced metrology and alignment methods
Rob Mundella, i3 Microsystems (Justin Borski, i3 Microsystems; Sylvain Misat, Peter van der Krieken, Jeroen de Boeij, Michiel van der Stam, Kulicke&Soffa Liteq B.V.) Nathan Whitchurch, Amkor Technology (Wei 
Advanced Insulation Materials for Next Generation High-Density Package  
Shohei Fujishima, Research Institute for bioscience Products & Fine Chemicals, Ajinomoto Co., Inc.
Progress in 3D Printed Multi-functional Ceramics
Eric MacDonald, University of Texas, El Paso 
4:30pm-5:00pm
Additive Manufacturing of Micro and Nanoscale Components for Heterogenous Integration and Advanced Packaging

Ahmed Busnaina, Nano OPS, Inc.

Squaring Off with M-Series Fan-Out Technology
Clifford Sandstrom, Deca Technologies (Benedict San Jose, Deca Technologies; Jen-Kuang Fang, Ping-Feng Yang, Sheng Feng-Huang, Ping-Ching Shen, ASE)  
Kitabatake, Rintaro Ishii, Katsuyuki Hayashi,

More than Moore with Silicon Photonics Chiplets In Package (SCIP)
C. Mike Newton, nScrypt/Sciperio (Anand Kulkarni, Kyle Stoodt, Siemens; Emily Sassano, Jason Benoit, Sciperio)Raghunathan, Broadcom

5:00pm-5:30pm
Novel IR Laser Debonding for Heterogeneous Integration and 3D Integration
Thomas Uhrmann, EV Group (Peter    Urban, Markus Wimplinger, Boris Povazay, Julian Bravin, Bernd Thallner)
Defluxing of Copper Pillar Bumped Flip Chips
Ravi Parthasarathy, ZESTRON Corporation (Umut Tosun)
Reliability Investigations in Printed Electronic Assemblies
Beihan Zhao, University of Maryland (Hisham Abusalma, Abhijit Dasgupta, University of Maryland; Edwin Quinn, Laboratory for Physical Sciences; Andres Bujanda, Army Research Lab)
5:30pm-6:30pm

Exhibit Hall Reception Sponsored by:     






Tuesday Evening Panel Discussion

6:30pm-8:00pm

(ROOM 107-108)

Sponsored by:



PANEL DISCUSSION on

PACKAGING CHIPLETS:
OPPORTUNITIES AND REMAINING CHALLENGES



Moderator
E. Jan Vardaman, President and Founder, TechSearch International, Inc.

Panelists:

Choon Lee, JCET Group | Chief Technology Officer
Chris Scanlan, Besi Switzerland AG | Senior Vice President Technology


Additional Panelists Soon



Wednesday, March 15th


GBC Keynote & Plenary Session

(ROOM 107-108)

Sponsored by:




IMAPS Global Business Council (GBC)


Welcome to the Global Business Council (GBC) Keynote & Plenary Session on

BUILDING THE ECOSYSTEM: TRANSITIONING FROM RESEARCH TO MANUFACTURING


7:00am-6:00pmRegistration
10:00am - 4:30pmExhibit Hall Open
(Wassaja Ballroom)
7:00am-8:00am

Continental Breakfast Sponsored by:



GBC Opening Comments:
GBC Chair: Lee Smith, Applied Materials

GBC SPEAKERS:

Hidenori Abe, Showa Denko
Madhavan Swaminathan, Georgia Institute of Technology
Sylvie Joly, CEA-Leti
Scott Sikorski, ASIC (IBM)

Followed by a panel discussion - additional agenda details soon


12:35pm-2:00pm

Lunch Break in the Exhibit Hall Sponsored by:

  


Wednesday Afternoon Sessions



  

HETEROGENEOUS 2D & 3D INTEGRATION Track

FAN-OUT, WAFER LEVEL PACKAGING
& FLIP CHIP Track

NEXT GEN APPLICATIONS Track


WP1: HYBRID Cu BONDING & MATERIALS
Chairs: Danny Singh, Intel Corp.; Steffen Kröhnert, ESPAT-Consulting
WP2: FLIP CHIP TECHNOLOGY 
Chairs: Danny Brady, Amkor Technology ; Knowlton Olmstead, Mercury Systems
WP3: ADVANCES IN 5G AND MEMS PACKAGING
Chairs: Vidya Jayaram, Intel Corp.; Jaewook Seok, Qualcomm
2:00pm-2:30pm

Advanced IC Substrates for Heterogeneous Integration
Venkata Mokkapati, AT&S (Rozalia Beica)

Fluxless Thermocompression Bonding of High Density Interconnects Via In-Situ Oxide Reduction as an Alternative to Hybrid Bonding
Bob Chylak, Kulicke & Soffa Industries (Andreas Marte, Horst Clauberg, Tom Colosimo)
Solutions for Low Cost, Near Hermetic Air Cavity Packages
Don Zyriek, RJR Technologies, Inc.
2:30pm-3:00pmHigh-yield Fabrication of Thin Glass Interposers
Shelby Nelson, Mosaic Microsystems, LLC (David Levy, Kyle Liddle, Patrick Borrelli)
Experiment-Simulation Correlation of a Flip Chip Package with Non-Uniform Power Distribution 
Eric Ouyang, JCET (Xiao Gu,YongHyuk Jeong, Michael Liu, JCET; WeiKun He,Andras Vass-Varnai, Siemens)
RF Packaging and Design for Development of High Performance 5G mmWave Modules
Ivan Ndip, Fraunhofer IZM (Thi Huyen Le, Kavin Murugesan, Uwe Maass, Michael Kaiser, Martin Schneider-Ramelow)
3:00pm-3:30pmChip to Wafer Hybrid Bonding Development for High Volume Manufacturing
Jonathan Abdilla, Besi (Guan Huei See, Raymond Hung, Ruping Wang, Arvind Sundarrajan, Applied Materials; Benedikt Auer, Besi)

Toward Thinner and Higher Heat Dissipation Advanced Chip Embedded Power Supply Module Packaging    
Katsuhiro Takao, AOI Electronics (Atsushi Kuroha, Ichiro Kohno, Takashi Suzuki, Yoshiaki Aizawa)

Final Finishes for Low Signal Loss: Layer Properties and Reliability of Final Finish Systems Without Nickel
Britta Schafsteller, MKS Instruments – MSD, Atotech Deutschland GmbH & Co KG (Mario Rosin, Dirk Tews, Gustavo Ramos)
3:30pm-4:30pm

Break in the Exhibit Hall
(Wasaja Ballrom)


4:30pm-5:00pm3D integration of Detector and ROIC through Wafer Bonding
Iqbal Ali, Cactus Materials, Inc. (Wey Lyn Lee, Brad Lenzen, Rafiqul Islam)
A Novel 2D/3D X-ray Microscopy Alignment and Inspection Solution for Thermocompression Bonding (TCB) in a Highly Integrated Flip Chip Fan-Out Wafer Level Package (FO-WLP)

Martin Kainz, Besi Austria GmbH (Johannes Ruoff, Holger Blank, Carl Zeiss SMT GmbH; David Taraci, Carl Zeiss Microscopy)

Glass Package and Through Glass Via (TGV) for MEMS
Aric Shorey, Menlo Microsystems (Chris Keimel)
5:00pm-5:30pmCreating Systems from Chiplets – Next Generation Integration Driven by Hybrid Bonding
Robert Patti, NHanced Semiconductors,Inc.
Validating Flip Chip Package Models through Experimental Deflection Measurements                 
Kevin Cox, Tektronix Component Solutions (Jason Krantz, Steven Tonthat, Matt Borden)
Hermetic package for MEMS mirror
Davide Rotta, CamGraPhIC Srl (Marco Chiesa, CamGraPhIC Srl; Marco Del Sarto, Luca Maggi, Amedeo Maierna, STMicrolectronics; Antonella Bogoni, Sant’Anna School of Advanced Studies)
5:30pm-6:00pmHybrid Bond Interconnect for Advanced Packaging Solutions
Thomas Workman, Adeia Inc. (Gill Fountain, Laura Mirkarimi, Guilian Gao, Jeremy Theil, Bongsub Lee)
Optimizing New Power Switch Technology Using Flip-Chip Assembly
Sam Sadri, QP Technologies (Jiankang Bu, Ideal Power)
5G mmWave Antenna in Package based on Chip last Fan-out RDL Interposer Technology
Lewis Kang, nepes Corporation





Poster Session Happy Hour
+ 3D InCites DEI Fund Night


Outside on Patio Overlooking Desert (weather permitting)

6:00pm-8:00pm






IMAPS POSTER SESSION HAPPY HOUR 
& 3D InCites DEI FUND NIGHT


Session Chairs: 
Pui Leng Low, onsemi; Hongbin Yu, Arizona State University 


Poster Session & Happy Hour Sponsored by:





Normalized Crack Length - A Means for Evaluating The Relative Risk of BMV Failure    
Roger Massey, MKS Atotech (Tobias Bernhard, Kilian Klaeden, Sebastian Zarwell, Edith Steinhaeuser, Sascha Dieter)


Warpage and Reliability Study of Large Size XDFOITM FO-MCM fcBGA    
Danfeng Yang, JCET Group (Allen Xu, Nokibul Islam, Coco Xu, Yaojian Lin)


Pillars of Wafer Temperature Uniformity and Tuning for sub-10 Reflow Applications    
Vladimir Kudriavtsev, Yield Engineering Systems (YES) (Lei Jing, Tapani Laaksonen, Zia Karim, Chris Lane)


High-Speed Performance Validation Testing of Die-to-Die Interconnects in High-Density Fan-Out Package    
Cindy Muir, Intel (Beth Keser, Carlton Hanna, Bernd Waidhas, Abdallah Bacha, Hui Zhang)


Launching the full potential of 3D IC with front-end architectural planning
Anthony Mastroianni, Siemens DISW (Gordon Allan)

Incorporating Hierarchical Construction for Advanced IC Packaging

Christopher Cone, Siemens EDA (Edward Hudson)

Winning with 2.5/3D IC starts with a system-level golden netlist
Tarek Ramadan, Siemens DISW (Mike Walsh)


RF Heterogeneous Integration using Photosensitive Glass Ceramics
Jeb Flemming, 3D Glass Solutions, Inc (Kyle McWethy)


From Manhattan to Advanced Package Design
Kyle Fraunfelter, Siemens (Greg Arnot)


Engineered Reliability – Safeguarding Electrical Components and Devices with Nanocoating Technology
Richard Weiland, HZO Inc. (Dan Pulsipher)


MaxQFP TM Exposed Pad (MaxQFP-EP): A thermally enhanced MaxQFPTM platform
Chu-Chung (Stephen) Lee, NXP Semiconductor Inc (Penglin Mei, XS Pang, JZ Yao, Andrew Mawer, Tu-Anh Tran)


The Science Of Adhesion - Insights To Understanding Adhesive Performance
Douglas Katze, Henkel Corp (Yuan-David Zhao, Henkel Corp; Rose Roberts, Brighton Science)


A Comprehensive Study of Surface Finishes for High Frequency/High Speed Applications
Frank Xu, MacDermid Alpha Electronics Solutions (Martin Bunce, Jim Watkowski, Anna Lifton, Raghu Raj Rangaraju, Rommel Bumagat)


ALSO IN SESSION WP2: FLIP CHIP TECHNOLOGY
Toward Thinner and Higher Heat Dissipation Advanced Chip Embedded Power Supply Module Packaging    
Katsuhiro Takao, AOI Electronics (Atsushi Kuroha, Ichiro Kohno, Takashi Suzuki, Yoshiaki Aizawa)


ALSO IN SESSION TA2: DESIGN & TECHNOLOGY
Cost Analysis of Fan-out Processes for Chiplet Packaging
Amy Lujan, SavanSys Solutions LLC


   
 

2023 3D INCITES DEI FUND NIGHT



Thursday, March 16th

7:00am-11:30am

Registration

7:00am-8:00am

Continental Breakfast Sponsored by:

     

8:00am-8:10am

Room 107-108

OPENING COMMENTS

General Chairs: Nokibul Islam, JCET Group; Scott Hayes, NXP Semiconductors

Plenary/Keynote Sessions Sponsored by:


8:10am-8:55am

KEYNOTE 3

DRIVING ADOPTION OF ADVANCED IC PACKAGING IN AUTOMOTIVE APPLICATIONS

For years automotive semiconductors, have been governed by small, low power Integrated Circuits (ICs) purpose built for specific functions. These Microcontroller Units (MCUs), deployed on the edge of the compute topology are typically low-power, low-performance parts. Built on legacy nodes (130nm+) on well-established packaging technology (often wirebond die on QFN-style packages), they demonstrated incremental improvements from a silicon and packaging perspective. With the adoption of software defined vehicles (SDV), the evolution of advanced driver assist systems (ADAS), and feature rich in-vehicle infotainment (IVI), the per vehicle compute power has grown exponentially per vehicle, colloquially, known as data centers on wheels. With this growth has come the need to adopt newer packaging techniques to improve system latency, bandwidth, compute power, and IP integration and reducing system footprint via 3D stacking – all fabricated on leading edge nodes. 
Advanced packaging has seen tremendous growth and adoption in the data center and client ecosystems – the next hurdle is addressing the safety and reliability focused requirements of automotives; extended useful lifespan of 10yrs+, and weathering harsher environmental conditions of thermal extremes, vibration, and EMC, and mixed IP integration. This talk will address the areas of focus for adopting heterogenous integration and advanced automotive packaging for automotives such as, qualification and formulation of materials to minimize traditional packaging yield concerns, introduction of new thermal interface materials aligned with new liquid cooled ECUs and testing to ensure zero defects across chiplets and memory; with broader test coverage and the adoption of Known Good Die (KGD). Additionally, the talk will cover the importance of driving industry standardization regarding die-to-die communication protocols, form factors, power delivery, system integration, and qualifying/enveloping new failure modes from the current baseline AEC-Q100 requirements brought on by various 2.5D and 3D packaging.

Bassam Ziadeh, General Motors
Bassam Ziadeh is a Global Technical Specialist at General Motors responsible for advanced package architecture roadmap and strategy definition. He was a technologist at Intel from 11 years working on inventing and developing novel technologies and architectures for advanced packaging prior to moving to General Motors to put these technologies into action and drive broader industry adoption. He received his Bachelors from the University of Jordan in 2010 and Masters from Arizona State University in 2011. He has over 15 US and International patents in the field of packaging and process technology and member of the UCIe Consortium.


8:55am-9:40am



KEYNOTE 4

EXTENDING MOORE’S LAW WITH INTEGRATED PHOTONICS

The insatiable growth in computing needs, coupled with the end of Denard Scaling and the slowdown of Moore’s Law, is resulting in a major shift across the industry towards a chiplets-based product architecture. Solutions that enable the heterogeneous integration of disaggregated silicon at high data rates and low power are becoming increasingly important. Silicon photonics based interconnect solutions play a critical role in enabling this integration.

Nicholas Harris, Lightmatter
With over 30 patents and 70 publications in journals including Nature, Nature Photonics, and Nature Physics, Nicholas’ work on quantum and classical information processing with integrated photonics has helped launch the international research field of programmable photonics. Nicholas has been recognized by the MIT Technology Review through the prestigious Innovators Under 35 Award. He received his doctorate in Electrical Engineering and Computer Science at the Massachusetts Institute of Technology where he was a National Science Foundation Graduate Research Fellow and later worked as a Postdoctoral Fellow through the Intelligence Community Postdoctoral Fellowship.

9:40am-10:00am

Break in Foyer Sponsored by

Thursday Morning Sessions




  
HETEROGENEOUS

2D & 3D INTEGRATION Track

FAN-OUT, WAFER LEVEL PACKAGING
& FLIP CHIP Track

NEXT GEN APPLICATIONS Track


THA1: 3D TECHNOLOGY & DESIGN
Chairs: Sanketh Buggaveeti, Infinera; Hongbin Yu, Arizona State University 
THA2: SUBSTRATE TECHNOLOGY
Chairs: Christo Bojkov, Qorvo ; Mark Kuhlman, Qualcomm
THA3: IMPROVING RELIABILITY IN ELECTRONICS
Chairs: Oliver Baltazar, Microchip; Ao Wang, Intel Corp.
10:00am-10:30amAI, ML and DL applications for semiconductor package design and verification
John Ferguson, Siemens DISW (Per Viklund)
High Speed Acid Copper Plating for IC Substrates
Sean Fleuriel, MacDermid Alpha Electronics Solutions (Kesheng Feng, Confesol Rodriguez, MacDermid Alpha Electronics Solutions; Robert Moon, Delores Cruz, Jonathan Hander, ASMPT-NEXX)    

TBD
Speaker Info Soon

10:30am-11:00am
Enabling Co-Design for 3D Heterogenous Integrated Packages

John Park, Cadence Design Systems

Low Loss/Low Modulus/Low CTE Semiconductor Carrier Packaging Thin Core Substrate Material
Caleb Ancharski, AGC Multi Material America (Thomas McCarthy, Preeya Kuray, Mark Derwin)    
Processing and Reliability Testing of a Copper Pressure Sinter Paste for use in High Power Module, Die Attach applications
Dean Payne, Indium Corporation (Min Yao, Hongyun Li)
11:00am-11:30am
TBD
Speaker Info Soon
Advanced IC Substrate Deformation and Pattern Distortion Analysis to Validate the Use of an Extremely Large Exposure Field Fine-Resolution Lithography solution
Keith Best, John Chang, Onto Innovation (Corey Shay, James Webb, Timothy Chang)    
Cu Wirebond Technology in 16FFC High Performance Automotive Radar Processor with IR Drop Reduction Methodology
Tu-Anh Tran, NXP Semiconductor (Jasmine Lim, Y.K. Au, M.J. Song, Mollie Benson)
11:30am-12:00pm
TBD
Speaker Info Soon
Advanced Glass Carriers for Buildup Structure Warp Control and Wafer Ultra-thinning    
Jay Zhang, Corning Inc. (Andy Teng, Christina Yu)

OSAT Production Testing of 5G, Power Discretes & 3D packaged ICs
Vineet Pancholi, Amkor Technology

12:00pmCONFERENCE ENDS



FOUNDATION GOLF OUTING AT 1:15PM 


HIKE FOR DEI

If you’re not participating in the golf tournament, why not join us for a guided, afternoon hike in the nearby McDowell Sonoran Preserve? All proceeds benefit the 3D InCites DEI Fund, established to help tech start-ups owned by women and under-represented minorities grow and thrive.

When: Thursday, March 16 from 12:30pm-4pm

Cost: $75 (includes transportation from We ko Pa Resort)

All proceeds benefit the 3D InCites DEI Fund