Device Packaging Agenda

CONFERENCE PROGRAM AGENDA


IMAPS is pleased to present the DEVICE PACKAGING CONFERENCE. Feature presentations, panel discussions, GBC and PDCs are listed below! 

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Tuesday, March 8th

7:00am-7:00pm

Registration

7:00am-8:00am

Continental Breakfast Sponsored by:


8:00am-8:20am


OPENING COMMENTS

General Chair: Prasad Dhond, Amkor Technolgy

Plenary/Keynote Session Sponsored by:


8:20am-9:05am


KEYNOTE 1

FUTURE OF PACKAGING
Moore's law has been the driving engine for science, technology, manufacturing, hardware, software, systems, and applications, contributing to the prosperity of thousands of individuals and 100s corporations in dozens of countries. As Moore's Law benefits begin to slow down, not for the doubling of transistors but for decreasing transistor speeds and the resulting slower computing performances, it is becoming clear that packaging must play a very critical and strategic role, unlike in the past. Prof. Tummala referrers to it as the next Moore‘s Law. Just like Moore‘s Law has both doubling of transistors and simultaneous cost reduction, from node to node every 18-24 months, Moore‘s Law for systems packaging or interconnections has been doing the same. Interconnections have been driven by computing systems and within computing systems, between logic and memory for the highest bandwidth and power efficiency.

The new era of artificial intelligence, mimicking the human brain with several orders better computer performance, is yet another reason for the next Moore's Law. The human brain is the ultimate systems packaging for the highest performance in the smallest size with the lowest power. Moore's Law for Packaging therefore must duplicate this architecture. The packaging or I/Os has historically evolved from DIPs in the 1970s with 16 IOs, QFP in the 1980s with 64 I/Os, ceramic packages in the 1990s with more than 500 I/Os, laminate packages in excess of 1000, and silicon packages approaching 200,000. Artificial intelligence mimicking the human brain may need several orders of magnitude.

Currently, the best Moore's Law for packaging is with wafer-based silicon packaging. But silicon-based packaging has many limitations at the material, device, circuit, and system levels. This talk describes the future need and potential opportunities to address this need.

Rao Tummala, Georgia Tech - Emeritus Professor
Rao Tummala is a Distinguished and Endowed Chair Professor and Director Emeritus at Georgia Tech in the USA. He is well known as an industrial technologist, technology pioneer, and educator. Prior to joining Georgia Tech in 1993, he was an IBM Fellow and Director of Advanced Packaging Lab (APTL), pioneering such major technologies as the industry‘s first plasma display in the 1970s and the industry's first very large 100-chip package with direct copper and water cooling, very much like today's chiplet .As an educator, Prof. Tummala was instrumental in setting up the largest and most comprehensive Academic Center funded by NSF as the first and only NSF Engineering Research Center in Electronic Systems Packaging at Georgia Tech. Such a center, under his leadership, pioneered an integrated approach to System-On- Package research, education, and global industry collaborations. It involved about 30 academic and full-time research faculty, 200 Ph.D. and MS students, and 50-70 industry and academic collaborators from the US, Europe, Japan, Korea, India, and Taiwan. It educated thousands of packaging engineers in classrooms and hands-on labs, and produced more than 1000 engineers with Ph.D., MS, and BS degrees, supplying to every major electronics company in the US

In addition, he is a distinguished Alumni of the Indian Institute of Science, Bangalore, India, the University of Illinois, and the Distinguished Faculty of Georgia Tech. He is a member of NAE, and a fellow of IEEE, IMAPS, and American Ceramic Society. He was the President of IEEE CPMT and IMAPS Societies. He has been an advisor to many semiconductor and system companies, and universities. For his legacy, life-long contributions, IEEE named him as one -in- generation of technologists and the Father of Modern Packaging, creating a Technical Field Award in his name-- IEEE Rao Tummala Electronics Packaging Award.

9:10am - 9:55am

KEYNOTE 2

ADVANCED PACKAGING: ENABLING MOORE'S LAW'S NEXT FRONTIER THROUGH HETEROGENEOUS INTEGRATION
With chiplet architectures becoming mainstream, and recognized as fundamental to enabling the continued economically viable growth of power efficient computing, advanced packaging technologies and architectures are becoming more critical to enabling Moore‘s Law‘s next frontier through heterogeneous integration. In this tutorial, we will cover the advanced package architectures being enabled by AMD to enable PPAC (power, performance, area and cost) improvements as well as enable heterogeneous architectures. The direct Cu-Cu bonding technology used in AMD‘s 3D VCache architecture will be detailed and compared to industry standard 3D architectures for PPAC benefits. Other technologies that are being enabled to advance high performance computing architectures will also be previewed.

Raja Swaminathan, AMD - Senior Fellow
Dr. Raja Swaminathan is a Senior Fellow at AMD responsible for package architecture and advanced technology strategy and development. He was a package architect at Intel for 13 years, moved to Apple to architect their new silicon package architectures before moving to AMD to drive their industry leading chiplet architecture integration. He received his Bachelors‘ from IIT Madras in 2000, PhD from Carnegie Mellon in 2005. He has over 35 US patents in the field and he is an IEEE Senior Member.

9:55am-10:00am
CONFERENCE LEADERSHIP RECOGNITION

General Chair: Prasad Dhond, Amkor Technology

10:00am-6:30pm
EXHIBITION OPEN

(Wasaja Ballroom)

10:00am-10:30am
Break in the Exhibit Hall Sponsored by:

Tuesday Morning Sessions

  

HETEROGENEOUS

2D & 3D INTEGRATION Track

FAN-OUT, WAFER LEVEL PACKAGING
& FLIP CHIP Track
AUTOMOTIVE, 5G &
NEXT GEN APPLICATIONS Track
TA1: 2D/3D  APPLICATION & DESIGN
Chairs: Suresh Jayaraman, Amkor Technology
TA2: FOWLP & FLIP CHIP: PROCESS
Chairs: Craig Bishop, Deca Technologies; Michael Vincent, NXP Semiconductors
TA3: iNEMI INVITED SESSION:
5G/MMWAVE PACKAGING: SOLVING HIGH FREQUENCY MATERIALS CHARACTERIZATION CHALLENGES

Chairs: Urmi Ray, iNEMI
10:30am-11:00am3D Packaging versus 3D Integration. Is there really a difference?
John Park, Cadence Design Systems
Empowering Front-End Cellular Innovations with Advanced SiP Solutions
Curtis Zwenger, Amkor Technology
Industry Challenges for Low Loss Measurements 
Urmi Ray, iNEMI; Say Phommakesone, Keysight
11:00am-11:30amHeterogeneous IC Packaging, Optimizing Performance and Cost
Michael Kelly, Amkor Technology, Inc. (Dave Hiner, George Scott, Doug Scott, Kevin Engel)
FOWLP Thermal Debonding: Easing Manufacturing Constraints                 
Debbie-Claire Sanchez, ERS electronic GmbH
Key Highlights from iNEMI 5G Project
Michael Hill, Intel Corp.
11:30am-12:00pmHeterogeneous Integration with 3D Packaging
Rahul Agarwal, Advanced Micro Devices, Inc. (Patrick Cheng, Priyal Shah, Brett Wilkerson, Raja Swaminathan)
Direct Bonding of Glass to Si Using Surface Activation at Low Temperature
Jay Zhang, Corning Inc. (Dennis Bumueller, Suss Microtec)
5G Electronics: Bridging the Measurement Challenges
Magorzata Celuch, QWED; Marzena Olszewska-Placha
12:00pm-12:30pmDesigning Silicon Interposers for 2.5/3DIC Heterogeneous Integration - Meeting Foundry and OSAT Requirements       
Chris Cone, Siemens EDA (Jamie Metcalfe)
Cost-effective High-density Fan-Out Chip on Substrate using M-Series™ and Adaptive Patterning® Technology
Robin Davis, Deca Technologies (Benedict San Jose, Deca Technologies; John Hunt, ASE US Inc.; Chia-Pin Chen, ASE Global)
mmWave Reference Material Development at NIST
Nathan Orloff, NIST

12:30pm-2:00pm

Lunch Break in Exhibit Hall Sponsored by:


Tuesday Afternoon Sessions

  HETEROGENEOUS 2D & 3D INTEGRATION TrackFAN-OUT, WAFER LEVEL PACKAGING
& FLIP CHIP Track
AUTOMOTIVE, 5G &
NEXT GEN APPLICATIONS Track
TP1: 2D/3D  TECHNOLOGY
Chairs: Rahul Agarwal, AMD
TP2: FOWLP & FLIP CHIP: EQUIPMENT / MATERIALS
Chairs: Knowlton Olmstead, Amkor Technology; Scott Hayes, NXP Semiconductors
TP3: SILICON PHOTONICS: the PATH AHEAD
Chairs: Vik Chaudhry, Amkor 
Technology
2:00pm-2:30pm3D Packaging: MEMS and Sensor Point of View
Marco Del Sarto, STMicroelectronics
EMI Shielding for System in Package Using Spray Coating and Silver Particle-Free Ink
Sima Hannani, Electroninks Inc. (Garret McKerricher, Melbs Lemieux)
More than Moore with Optical Chiplet Packaging - TBD
Vivek Raghunathan, Broadcom
2:30pm-3:00pmMaskless Direct Write Lithography for 3D Wafer-level-system-integration
Frank Windrich, Fraunhofer IZM-ASSID (Achim Jehle, Sven Preuss, Heidelberg Instruments Mikrotechnik GmbH)
Electrochemical Plating System Development of Nano-twinned Cu for Multiple WLP Features
Jianwen Han, MacDermid Alpha Electronics Solutions (Pingping Ye, Stephan Braye, Kyle Whitten, Cai Wang, David Shaffer, Adam Letize, Brian Gokey, Thomas Richardson, Elie Najjar)
Holistic Transformation in High
Volume Manufacturing of Data
Center Transceivers
Tolga Tekin, Fraunhofer IZM
3:00pm-3:30pmLaser Processing of Molybdenum Substrates and Polyimide Layers for Extreme Environment Electronics
Sherman Peek, Auburn University (George Hughes, John Sellers, Masoud Mahjouri-Samani, Mark Adams, Michael Hamilton)
The Grinding and Polishing Technology for Various Materials
Bob Pinto, Okamoto Corporation (Takeru Inoue, Okamoto Machine Tool Works)
Advanced Packaging Technology
for High Density Silicon Photonics 
Transceiver Engines
Peter De Dobbelaere, Cisco
3:30pm-4:00pmBreak in Exhibit Hall
4:00pm-4:30pmMaskless Laser Direct Imaging & Adaptive Patterning Solution for Fan-Out Heterogeneous Integration
Clifford Sandstrom, Deca Technologies (Timothy Olson)
Liquid Metal Embedded Elastomers (LMEEs) 
as TIM1 with Highly Reliable & Extremely Low Thermal Resistance Performance   
Navid Kazem, Arieca Inc. (Vivek Singh, Philip Marzolf, Jeffery Gelorme, Carmel Majidi)
Establishing a Packaging Ecosystem for GlobalFoundries Leadership Silicon Photonics Wafers – 2022 view
Dan Berger, GLOBALFOUNDRIES (Norm Robson, Ian Melville)
4:30pm-5:00pmThermal Performance Simulation of Heterogeneous Integration and Coupled Thermal-Mechanical Simulation of Large Body HDFO
Nathan Whitchurch, Amkor Technology (Wei Lin, Mike Kelly)
Thermal Interface Materials:  Effect of Physical Properties on Warpage in a Model Test Vehicle

Paul Morganelli, DuPont Electronics & Industrial Materials (Shourya Jain, Yusuke Matsuda, Jeff Meth, Lyndon Larson, Samantha Morelly)

5:00pm-5:30pm
New Development in Selective Surface Modification Materials with Promising Adhesion Performance

Ziwei Liu, Brewer Science, Inc. (Jinhua Dai)

Indium Alloy Termal Interface Materials for High-Power Lidded FCBGA Products
YoungDo Kweon, Amkor Technology (Mike Kelly)
5:30pm-6:30pm

Exhibit Hall Reception Sponsored by:     

Wednesday, March 9th

GBC Kenote & Plenary Session

(ROOM 107-108)

IMAPS Global Business Council (GBC)

Welcome to the Global Business Council (GBC) Keynote & Plenary Session on

US DOMESTIC CAPABILITIES FOR ON-SHORING
OF IC PACKAGING AND ASSEMBLY FOR DoD ACCESS

OPENING COMMENTS:
GBC Chairs:  Tom Goodman, Izinus Technologies; Rich Rice, ASE Group; Lee Smith, Consultant


7:00am-6:00pm
Registration
7:00am-8:00am

Continental Breakfast Sponsored by:


8:00am-8:15am
GBC OPENING COMMENTS

GBC Chairs: Thomas Goodman, Izinus; Rich Rice, ASE Group; Lee Smith, Consultant

8:15am-9:00am
KEYNOTE PRESENTATION TITLE
Keynote Speaker Soon

9:00am-9:30am
PRESENTATION TITLE
Speaker Soon
9:30am-10:00am
PRESENTATION TITLE
Speaker Soon
10:00am-10:20amQUESTION & ANSWER SESSION
10:20am-11:00amBreak in the Exhibit Hall
11:00am-11:30am
PRESENTATION TITLE
Speaker Soon
11:30am-12:00pm
PRESENTATION TITLE
Speaker Soon
12:30pm-12:35pm
GBC SESSION CLOSING REMARKS

12:35pm-2:00pm

Lunch Break in the Exhibit Hall Sponsored by:


Wednesday Afternoon Sessions

  HETEROGENEOUS 2D & 3D INTEGRATION TrackFAN-OUT, WAFER LEVEL PACKAGING
& FLIP CHIP Track
AUTOMOTIVE, 5G &
NEXT GEN APPLICATIONS Track
WP1: 2D/3D TECHNOLOGY: MATERIALS & DESIGN
Chairs: Dongshun Bai, Brewer Science
WP2: FOWLP: TECHNOLOGY & DESIGN
Chairs: Rameen Hadizadeh, Cirrus Logic; Curtis Zwenger, Amkor Technology
WP3: PRINTED ELECTRONICS
Chairs: Robert Dean, Auburn University; Eric MacDonald, University of Texas
at El Paso
2:00pm-2:30pmNovel High Temperature Tape for Bump Protection with Easy Debonding
Jimmy Wang, 3M (Robin Gorrell, Benson Chen, Jian-Kuan Wu, Wei Zou, Joann Wang-Ostrom)
FOWLP and Flip Chip Cost Comparison: Impact of the Supply Chain Crunch
Amy Lujan, SavanSys Solutions LLC
Direct Digital Manufacturing (DDM)
workflow for Printed Circuit
Structures (PCS)
C. Mike Newton, nScrypt, Inc. (Anand 
Kulkarni, Kyle Stoodt, Siemens
Technology; Jason Benoit, Sciperio, Inc.)
2:30pm-3:00pmPhoto-Imageable Dielectrics Enabling Structured MEMS and 2.5D / 3D Bonding Schemes
David Danza, DuPont Electronics & Industrial (Colin Hayes, Kevin Wang, Greg Prokopowicz, Paul Berry, Masaki Kondo, Michael Gallagher)
Advanced Fanout Embedded Bridge Packaging Technology for Chiplets Integration  
Lihong Cao, ASE Group (Teck Chong Lee, Yung-shun Chang, Sheng-Wen Yang, Yen-Liang Huang, I-Ting Lin, Yihsien Wu)
Geometrically-Complex 3D Printed
Alumina Substrates for Electronics
Eric MacDonald, University of Texas
at El Paso (Pedro Cortes, Youngstown
State University)
3:00pm-3:30pmLow-Loss Photosensitive Polymeric Dielectric Materials for Millimeter Wave and Terahertz Applications
Mei Dong, Brewer Science (Baron Huang, Duo Tsai, Rama Puligadda)

Scaling Down while Scaling Up with M-Series? Fan-out & Adaptive Patterning
Clifford Sandstrom, Deca Technologies (Timothy Olson)

Inkjet-/3D-/4D-Printed 'Zero-Power' Flexible Wireless 
Ultrabroadband 
Packages & Modules for IoT, SmartAg and SmartCities
Manos Tentzeris, Georgia Tech
3:30pm-4:30pm

Break in the Exhibit Hall

(Wasaja Ballrom)

4:30pm-5:00pmDensely Packed Electronic Systems
Peter Salmon, Salmon Engineering
High Speed Transmission Characteristics of RDL Interposer Using Low Loss Dielectric Materials

Satoru Kuramochi, Dai Nippon Printing

Aerosol Jet Printed Interconnects for Millimeter-Wave Components
Bryan Germann, Optomec
5:00pm-5:30pmHeterogeneous Integration of Chiplets, Lego-like IP for More Than Moore
Keith Felton, Siemens DISW
P-WLCSP: 6-Side Protected WLCSP                   
Douglas Hackler, American Semiconductor, Inc.
Viability of 3D Printing Methods as a Solution for Field-repairs of Electronic Systems
Abhijit Dasgupta, University of Maryland (Christopher Riso)
5:30pm-6:00pmDesign and Analysis Challenges of 3D Multi -Chiplet Heterogenous Architectures
John Park, Cadence Design Systems, Inc.
Improving Reliability of Fan-OUT Wafer Level Package Through Doping of Lead-Free Solder Balls
Bernhard Rieder, Infineon (Walter Hartner, Gerhard Haubner, Martin Richard Niessner, Wenbo Yuan)
Laser-Based  Additive Nanomanufacturing 
of Printed Electronics on Rigid and Flexible Substrates
Zabihollah Ahmadi, Auburn University (Seungjong Lee, Raymond Unocic, Nima Shamsaei, 
Masoud Mahjouri-Samani)

Poster Session Happy Hour

Outside on Patio Overlooking Desert

6:00pm-7:00pm

POSTER SESSION HAPPY HOUR

Improving Semiconductor Manufacturing Yield with Chip-Level FEA
Tyler Ferris, Ansys (Greg Caswell)

Toward Ultra-Precision Surface: Polishing Performance of Dynaqualdiamond Slurry on the Advanced Optoelectronics Material
Tong Liu, Qualdiamond High Tech Inc (Biz Mohammed, Qian He)

Gold Wire Bonding vs. Coated Silver Wire Bonding
William Crockett, Tanaka USA (Dhiraj Bora, Silitronics)

Development of a Printed Ice Sensor for Use in a Printed Passive Wireless Sensor Tag

Robert Dean, Auburn University (Moriah Reed, Auburn University; Ian Small, NASA-MFSC)

Process Improvements for Reduced Yield Fallout during Tri-Temperature Package Test

Jerry Broz, International Test Solutions, a CMC Materials Company (Bret Humphrey)

Molecular Modeling of Solvent Compatibility in Polymer Packaging for Electronic Devices

Mohammad Atif Faiz Afzal, Schrodinger Inc (Alexander Goldberg, Andrea Browning, Shaun Kwak, Mathew Halls)


2020 3D InCites "Bonus Happy Hour" & Awards Ceremony

6:30pm-7:30pm
Immediately Following the Poster Session - Outside On Patio Overlooking Desert (Weather Permitting)

Thursday, March 10th

7:00am-11:30am

Registration

7:00am-8:00am

Continental Breakfast Sponsored by:

     

8:00am-8:10am

Room 107-108

OPENING COMMENTS

General Chairs: Prasad Dhond, Amkor Technology; Nokibul Islam, JCET Group

Plenary/Keynote Sessions Sponsored by:



8:10am-8:55am



KEYNOTE 3

HYBRID BONDING FOR THE NEXT GENERATION OF HIGH PERFORMANCE DEVICES
The electronics industry continues to pursue optimal performance for the insatiable consumer demand of computation intensive products like GPUs, CPUs and AI accelerators. While the monolithic system on chip approach promises exceptional performance, it is costly. The advanced packaging industry has responded to the challenge with 2.5D and 3D integration solutions that bridge the performance gap with heterogeneous integration. Hybrid bonding combined with chiplet architectures within 2.5D will enable the distribution of function and nodes across a chips within a module, providing a path toward more flexible product introduction and innovation.

The design and manufacturing of chip-to chip-communication is complex and has some technology dependencies. One technology limitation in realizing a monolithic performance with heterogeneous integration is solder interconnect scalability. Hybrid bonding is a revolutionary platform technology that solves the interconnect scalability problem and delivers enhance performance compared to the conventional Cu microbump.

The Direct Bond Interconnect (DBI®), more generally known as hybrid bonding, offers a performance boost that enables novel 3D architectures via disaggregation and chiplet implementation, in spite Moore‘s law slowing. The efficient interconnect between circuit functions at the wafer, die and package level, will fuel semiconductor company roadmaps for decades. The performance advantages, ease of integration of such a hybrid interconnect will be discussed in chip to wafer and chip to chip applications. The key areas of innovation anticipated to proliferate the technology within the entire advanced packaging supply chain will be presented.

Laura Mirkarimi, Xperi Corp. - VP of Engineering, 3D Portfolio and Bonding Technology
Laura Mirkarimi is VP of Engineering, 3D Portfolio and Bonding Technology at Xperi Holding Corporation, San Jose, California. She received a PhD in Materials Science at Northwestern U. Dr. Mirkarimi leads the 3D team at Xperi. Prior to joining Xperi, she developed electronic devices including ferroelectric memory, transparent conductors and photonic crystal resonators at Hewlett Packard Laboratories for 12 years. She holds more than 50 patents and 45 publications.

8:55am-9:40am



KEYNOTE 4

INTELLIGENT POWER AND SENSING SOLUTIONS FOR A SUSTAINABLE FUTURE
Vehicle electrification, autonomous driving, renewable energy and big data are enabling unprecedent changes in human life, and are pushing the technology to new limits. Those major evolutions require power electronics and sensing solutions, driven by optimum technology and packaging solutions to deliver maximum product efficiency. This talk will review recent progress in front end technology, packaging (discrete, power modules) and highlight the importance of system integration.

It will illustrate the challenges of simultaneously meeting a wide range of power density, product scalability, cost and reliability requirements, and are made possible by the ongoing progress in semiconductor research, engineering and manufacturing.

Jerome Teysseyre, ON Semiconductor – VP, Head of Package Development and Engineering
Jerome is having 22 years of experience in Package development. He holds a master in material sciences from Grenoble Institute of Technology.

He started his career at STMicroelectronics where he held several positions until 2014. Jerome managed ST‘s package assembly process and technology development group in Europe covering  the broad portfolio of mobile phone applications with BGA, System in Package, embedding, optical camera sensors   and smart power packages. From 2010 to 2014 Jerome lead Asian teams in charge of Wafer level fan in, fan out, Camera and optical sensor development and developed packaging south east Asia center of competency to support the growing automotive market needs. Among his function in Singapore, he developed the Next Generation E-WLB (fan out) in partnership with Statchippac and Infineon. Jerome moved to Fairchild in 2014 (acquired by onsemi in 2016) and shifted his focus to power semiconductor to enable differentiated package portfolio on automotive , industrial power modules and QFN - SIP migration for Cloud computing.

Jerome‘s team are focusing on the extension of automotive package portfolio and solutions for wide band gap.

9:40am-10:00am

Break in Foyer


Thursday Morning Sessions

  
HETEROGENEOUS

2D & 3D INTEGRATION Track

FAN-OUT, WAFER LEVEL PACKAGING
& FLIP CHIP Track
AUTOMOTIVE, 5G &
NEXT GEN APPLICATIONS Track
THA1: 3D TECHNOLOGY - PRINTING
Chair: Rafiqul Islam, Cactus
THA2: FLIP CHIP
Chairs: Danny Brady, Amkor Technology; Burt Carpenter, NXP Semiconductors
THA3: 5G MATERIALS – TBD
Chairs: Tu-Anh Tran, NXP Semiconductors;
Vidya Jayaram, Intel Corp.
10:00am-10:30amInkjet Printing in Semiconductor Packaging Technology
Joost Hermans, SUSS MicroTec (Wouter Brok)
How to Tailor Immersion Tin Plating for IC Substrate Applications  
Britta Schafsteller, Atotech Deutschland GmbH (Andreas Schatz, Gustavo Ramos, Hubertus Mertens, Moody Dreiza)
Demonstration of High Performance of N77 RF Filters on Corning Alumina Ribbon Ceramic
Chenggang Zhuang, Corning Incorporated (Shiwen Liu, Heather Vanselous-Barrett, Corning Inc.; Feng Ling, Lijun Chen, Xpeedic)
10:30am-11:00am
Micro Transfer Printing:  Massively Parallel Pick-and-Place of Ultra-Thin Die

Bob Conner, X-Celeprint (Bill Batchelor,David Gomez)

Solder Flux Evolution for Heterogeneous Integration
Evan Griffith, Indium Corporation (Sze Pei Lim)
LCP Substrate for Antenna in Package Integration
Andy Heinig, Fraunhofer IIS/EAS 
11:00am-11:30am
Wafer-level Integration Technologies enabling Advanced System Solutions in a Wafer Foundry

Stefan Ernst, X-FAB MEMS Foundry

Improvement of Micro-via Reliability
by Using a New Electroless Cu Plating
Zheng Zhang, Osaka University (Ming-Chun Hsieh, Jeyun Yeom, Aiji Suetake, 
Hiroshi Yoshida, Katsuaki Suganuma, Osaka University; Joonhaeng Kang, Okuno Chemical Industries Co.)
New Design of Patch-liked Dipole Antenna for Millimeter Wave 5G Application
Chia Chu Lai, Siliconware Precision Industries Co., Ltd (Sam Lin, Teny Shih, David Lai, Yu Po Wang)
11:30am-12:00pm
High-thruput Printing of Micro & Nanoscale 

Interconnects, Passive and Active Electronics for Heterogeneous Integration
Ahmed Busnaina, Nano OPS, Inc.

Build-up Materials with Low Insertion Loss/fine Pitch Wiring and Low Warpage Molding Material for Advanced Packages
Habib Hichri, Ajinomoto Fine-Techno USA Corporation (Yuka Shibata, Ryo Miyamoto)
Immersion Tin Plating Enabling Reliable Wettable Flanks on QFN Packages
Arjan Hovestad, Meco Equipment Engineers B.V. (Tarun Basu, Sytron Pte Ltd; Chris Scanlan, Besi Netherlands B.V.)
12:00pmCONFERENCE ENDS

FOUNDATION GOLF OUTING AT 1:00PM at SunRidge Canyon Golf Course

or

3D InCites Hike for DEI, Sponsored by KLA