Device Packaging 2021 PDCs


What are PDCs?

Professional Development Courses are supplemental two-hour classroom-style tutorials with a narrow educational focus taught by the best in the industry. The topics offered at DPC 2021 are designed to help attendees broaden their scope of knowledge.

Virtual Delivery

PDCs will be taught in a real-time, live atmosphere in a private zoom room between the instructor and course registrants. Questions will be taken in an interactive environment.

Each course will be taught during it's published date and time only. PDCs will not be available on-demand. Attendees agree and understand that their registration is for a real-time instructional course.

Device Packaging 2021 PDC Course Offerings

NEW! The 2021 PDC courses are offered each day of the virtual conference. Attendees must register for each course as an add-on to their overall symposium registration at $250 each. Attendees may select up to one course in each time slot. 

Make sure to review your preferred course's date and time slot before registration. Course fees are non-refundable.  


Course Fees and Inclusions

Course Fees: $250 per course.

Fees include access to the 2-hour course led by reputable industry leaders.
Virtual format only.  Printed materials will not be provided. 
These fees are non-refundable but may be transferred to another registrant prior to the start of the course. No transfers will be accepted once the course has begun. 

How to Register

  1. Click here to get started.
  2. Log into your member account or create a guest* account.
    *Remember! Member, Nonmember, Speaker, Chair, and Student event registrations include a one-year IMAPS membership. Make sure to populate your account thoroughly. Guest accounts will be converted to member accounts within 30 days of your event registration.
  3. Select the Device Packaging 2021 event. 
  4. Select your overall conference registration type (Member, Nonmember, Speaker, Chair, Student).
    Only planning to attend a PDC? Select "PDC Only" as your registration type. PDC-only registrants will not have access to additional conference content. 
  5. Choose your course(s) selection in the time slot drop-down boxes. Select up to one course per time slot.
  6. Check out. You will receive a confirmation email detailing your registration. 

If you need to add or change course selection(s) after completing a registration, please contact Shelby Moirano at 

Course Descriptions

Polymers For Wafer Level Packaging
Jeffrey Gotro, InnoCentrix, LLC


The course will provide an overview of polymers used in wafer level packaging and the important structure-property-process-performance relationships for polymers used in wafer level packaging.  The main learning objectives will be: 1) gain insights on how polymers are used in Fan Out Wafer Level Packaging, specifically mold compounds and polymer redistribution layers (RDL) 2) learn the key polymer and processes challenges in Fan Out Wafer Level Packaging including panel level processing, and 3) understand the types of polymers used in wafer level packages, including pre-applied and wafer applied underfills. We will cover in more depth the chemistries, material properties, process considerations for polymers used in wafer level packaging.  The course has been completely updated to include a detailed discussion of the polymers and polymer-related processing for Fan-Out Wafer Level packaging (such as chip first and chip last process flows).

Sensor Packaging
Robert Dean, Auburn University


Without modern electronic packaging technologies, many useful or even necessary sensors would not be able to be commercialized.  Packaging is an integral part of modern sensor technology and can account for as much as half of the cost of manufacturing a packaged sensor.  This PDC will convey the current state-of-the-art in packaging of sensors, and will primarily focus on the packaging of solid state chip sensors.  After an overview of current chip sensor technologies, I will discuss the unique characteristics and requirements for successfully packaging these types of sensors so that they possess the necessary access to the operating environment required for successful functioning, as well as the indispensable protection from the operating environment needed to achieve long term reliable operation.  Relevant sensor technologies will be discussed, such as MEMS inertial sensors (accelerometers, vibratory gyroscopes, and single-chip IMUs), MEMS pressure sensors, chemical sensor chips (relative humidity, moisture content, pH, electrical conductivity, conductimetric, etc.), temperature sensors, optical sensors, and more.  Each of these types of chip sensors possesses distinct packaging requirements, as well as unique vulnerabilities.  For example, MEMS inertial sensors are often hermetically packaged to isolate them from moisture, mechanical contact, dust, and exposure to harsh chemicals possibly present in their operating environment.  However, because they consist of microfabricated structures, these sensors may be sensitive to high frequency and/or high energy mechanical vibrations or acoustic signals that could be present in the intended operating environment.  If certain frequency components of these environmentally present signals couple through the hermetic package to the chip sensor, they could adversely affect the operation of the sensor by resonating the sensor's microstructures.  So, additional packaging structures may be required, beyond just hermetically sealing the sensor dice inside a package, to attenuate undesirable vibration or acoustic components.  Furthermore, in order to achieve sufficiently long operational lifetimes, the hermetic package may require a getter in order to maintain a desired pressure or gas chemistry inside the package for optimal sensor performance.  Another example is chemical chip sensors, which although they might be impervious to high frequency environmental vibrations or acoustic excitation, they may be very sensitive to dust accumulation or condensation on the active surface of the chip sensor, requiring this issue to be mitigated by the sensor package.  Similarly, optical sensors may require a transparent window in the package or package lid to be free of dust accumulation for optimal sensor performance.  Sensor packaging also affects other potentially important issues related to modern applications for chip sensors, such as the co-packaging of sensor and electronics chips, energy harvesting from the ambient environment to power the sensor, wireless data transfer to or from the sensor, sensors for biomedical applications, flexible sensors, and the roll of additive manufacturing related to sensor packaging.  These topics will also be covered in this PDC.

Fan Out Variations - Structures and Processes for Low and High Density 
John Hunt, ASE Group

Fan Out technology has evolved as an alternative package to meet the need for miniaturization of electronics, while also providing improved electrical interconnectivity.  Until around 2016, Fan Out was considered primarily a solution for low density packaging requirements.

The wide use of mobile and many IOT devices coming into use has driven the need for increased capability of data centers.  Fan Out technology is now in production for many of these applications.  It also enables the heterogeneous integration of die and memory with improved electrical performance and lower cost than traditional 2.5 packaging for these data center requirements. With the advent of chiplet packaging, fan out also offers a cost-effective solution for this combination of multiple die in a single package.

We will review how the integration of wafer level processing technologies and Flip Chip packaging structures have come together into recent advances in both low density and high-density Fan Out packaging. These packages are for automotive, IoT, advanced mobile and server applications. They can have higher levels of integration and sophistication than has ever been possible in the past.  A brief overview of the concept of Fan Out packaging and history of its evolution, and Fan Out developments to meet both low- and high-end applications will be included in this course.

Flexible Hybrid Electronics 2.0 
Subramanian Iyer, UCLA


Flexible Hybrid Electronics (FHE) has made a significant impact in medical electronics and wellness devices using the methods of classical packaging. However, the potential to go far beyond is significant, if we adopt advanced packaging techniques such as Fan-Out Wafer-Level Packaging. This tutorial will address the application space, material aspects, integration technology, energy storage and management as well as the semiconductor ecosystem needed to to take FHE to the next level. We will relate this to what is happening in the heterogeneous integration area and show how the dielet / chiplet revolution can have significant impact on FHE as well.        

The Evolution of Flip Chip Package Technology
Mark Gerber, ASE Group


This PDC course will provide a historical overview and background on the evolution of flip chip packaging as well as short market perspective on this platform. Mobile, Infrastructure, Automotive, High Reliability, Medical and High-Performance Network and Computing all rely on Flip Chip technology to enable their silicon solutions.  Although the use of new technologies such as Fan-Out hold promise for certain applications, flip chip advancements continue to challenge many new technology competitors from a price and reliability perspective and may end up driving hybrid approaches.  Interconnect structure, process flows, materials and package integration process methods for evolving Flip Chip applications will be discussed in detail. Understanding the trade-offs between the different bump structures and package platforms is key in determining the silicon device layout and the type of design rules that can be leveraged for new products. As part of this course, the assembly process details will be discussed and will include Mass Reflow, Thermo-Compression Non-Conductive Paste (TCNCP) bonding and Laser Assisted Bonding. Reliability aspects such as IMC formations and ways to address will also be covered as a key consideration for Interconnect decisions.      

3D Package Assembly and Technology for Mobile Devices 
Tom Dory, Fujifilm Electronic Materials USA

This PDC provides details on current and future assembly 3D packaging processes and technologies. The 3D IC and wafer-level packaging area is forecasted to grow to over $2.5 billion by 2016 driven by mobile devices including phone and tablet computers. Advanced packaging requirements require the evolution of back end manufacturing to become more process control driven. The 3D stacked die TSV packaging has advantages, but only in some market segments. In the cell phone market, stacking chips helps to minimize some of the interconnect issues between the logic and the memory chips. Wire bonding remains a key assembly method for 3D memory packages. This workshop will cover 3D and 2.5D (interposer) designs, 3D assembly flow, known good die, KGD, concerns, 3D package testing issues, supply line logistics, thermal management, logic bump out designs, wafer thinning and handling (thermal & laser debonding and residue removal) and interposers with microfluidics cooling built-in. The objective of this workshop is to provide the students with an overview of the technologies, materials, and processes involved in the latest 3D and 2.5D assembly processes.

5G mmWave Package Development Requirements and Solutions 
Urmi Ray

The fifth Generation (5G) mobile communication era is expected to address the insatiable need for data communication by introducing mmWave technology and protocols. The unprecedented latencies offered by 5G Networks will enable users to indulge in gigabit speed immersive services regardless of geographical and time dependent factors.

The key to enabling this architecture is packaging and system integration, especially involving an effective antenna structure and RFIC communication in cost-effective, small form-factor packages. As full speed development, demonstration and qualification of mmWave systems have accelerated in 2017, different design and packaging architectures are emerging.

This PDC will provide a comprehensive landscape of package development options including LTCC, eWLB/FOWLP as well as laminate based packaging. The specific requirements of materials and process needs (low dielectric material, copper roughness requirements) are discussed. Multiple different package structures are presented as case studies to demonstrate comparative performance of eWLB vs laminate packages. Product application spaces ranging from mobile/handheld to network infrastructures and automotive/satellite radars are highlighted. Key aspects and guidelines towards a cost/performance trade-off analysis will be summarized.

Chip Packaging Processes and Materials 
Syed Ahmad

The course presents manufacturing, materials, quality and reliability info in terms understandable to engineering and non-engineering personnel. Packaging characteristics and drivers will be outlined. Types of packages and critical differences among them and their applications will be discussed. The course will look at the design selection to meet use and application environments. Step-by step manufacturing flow for plastic packages will be presented as an example to understand the complexity of processes, materials and equipment involved in their manufacture. Advanced packaging will be introduced. Materials selection with respect to application environments will be discussed. Quality and reliability issues related to chip packaging and assembly and their solution will be outlined.          

System-in-Package (SiP) - System Solutions Through Miniaturization 
Mark Gerber, ASE Group

This PDC course will introduce the package platform SiP (System-in-Package) and how some companies are diversifying from SOC (System-on-a-Chip) to leverage heterogeneous silicon integration and package miniaturization to enable system level solutions. A short market perspective will be reviewed as well as how industry segments are leveraging SiP and how the OEM market is evolving and creating system level ecosystems to enabling content revenue- a key area of IOT. SiP general process flow details will be covered as well as key process considerations for yield improvements. In addition, a brief overview of some of the tools that may be leveraged to help miniaturize module solutions and improve performance. This class will also introduce several variations of the SIP platform using Fan-Out Wafer Level packaging and new embedded substrate technologies are also emerging as powerful future platforms to enable lower power and higher performance devices using solderless interconnects.

Introduction to Failure Analysis in Semiconductor Package Assembly
Tom Dory, Fujifilm Electronic Materials USA 

The workshop participants will receive an overview of failure analysis methods and reliability testing in assembly. Quickly finding and eliminating package defects and failures due to assembly issues is critical. Package reliability directly affects manufacturing yield, time to market, product performance, customer satisfaction and cost. A thorough understanding of product and technology reliability principles and mechanisms of failure is essential for assembly FA and integration engineers. Knowledge of defects and failure mechanisms enables a high yielding successful assembly process through material choices, package design, process optimization, and thermo-mechanical considerations. Each engineer needs to understand the impact of their choices and methods on the final product. This workshop will discuss, using examples, mechanical and thermal failure mechanisms in assembly and detection methods.

Flip Chip Package Technology and Assembly Processes 
Tom Dory, Fujifilm Electronic Materials USA

The objective of this PDC is to provide an improved understanding of current flip chip package options and assembly flows. This workshop will begin with a discussion of current flip chip assembly including fanout wafer level packaging (FOWLP) and 2.5 & 3D package assembly. We will then discuss the newer technology options and issues. Flip chip packaging assembly is not new, but newer device requirement require more connections between the die and package, a tighter bump pitch and more functionally in the package. Laptop computers, tablets and smart phones, using flip chip packaging with thinned die and thin packages are driving new assembly requirements.  All new technology drivers bring new challenges that will be discussed in this PDC. These assembly challenges include copper pillar bonding, bump stack material changes, tighter bump pitch, underfill flow and no-flow options, new under fill materials, thermal management with improved thermal interface materials (TIM), embedded passives, and die attach films. Also discussed are current wafer thinning process options including bonding and debonding to a carrier. Dicing and handling thin wafers and die will be covered. Newer bump materials will be discussed with their impact to flip chip or stacked die package assembly.

High-Speed LPDDR4X/5 Signal and Power Integrity
Advances in Mobile and Automotive Memory Systems

Sunil Gupta, Qualcomm Technologies, Inc 

This tutorial will focus on the Signal and Power integrity analysis of the LPDDR4X/5 memory system for mobile and automotive applications. All aspects of memory system consisting of SoC, DRAM, Package and PCB will be covered. The tutorial will give beginners and experienced engineers essential skills for successfully performing SI/PI analysis for their systems.

Topics that will be addressed:

1. Basics of memory devices: SRAM, DRAM (LPDDR/DDR/GDDR/HBM) and NAND.
2. Mobile and Automotive Memory systems.
3. SoC-DRAM PoP (Package-on-Package) and External memory system configurations.
4. Single-ended versus Differential signaling for I/O interfaces.
5. DRAM, memory device, supply rails.
6. Advanced packaging – FOWLP (Fan Out Wafer Level Packaging) for PoP mobile systems.
7. LPDDR5 new features summary.
8. Signal and Power integrity challenges and mitigation in LPDDR4X/5 system.
9. System memory modes – X16, X8 and mixed-mode.
10. Memory system timing budget breakdown.
11. SI components – Crosstalk, ISI (Inter-symbol Interference) and reflections.
12. PI components – SSN (Simultaneous Switching Noise) and PSIJ (Power Supply Induced Jitter).
13. Co-SIPI analysis, I/O schemes, terminations and FOM (Figure-of-Merit) using eye-apertures.
14. PDN (Power Delivery Network) frequency and time domain analysis results.
15. DBI (Data Bus Inversion) coding for SSN mitigation in memory system.
16. SI mitigation using techniques of NT-ODT (Non-Target On-Die Termination) and DFE (Decision Feedback Equalizer).
17. Link ECC (Error Correcting Code) and DRAM ECC for enhanced reliability.
18. Post-silicon validation and JEDEC compliance using ATE, bench, platform and debug tools.