Device Packaging 2020 Program

16th International Conference and Exhibition on

DEVICE PACKAGING

www.imaps.org/devicepackaging

March 2-5, 2020
WekoPa Resort
Fountain Hills, Arizona USA

 
Conference Program    Register        Speakers       Exhibitors       PDC Info       Hotel Info     Golf at DPC  
 
MONDAY, MARCH 2, 2020  --  Professional Development Courses (PDCs), Exhibitor Move-in, & Welcome Reception
7:00am-7:00pmREGISTRATION
 Room 103Room 102Room 104Room 105
MORNING COURSES:
10:00AM-12:00PM     
PDC 1:   CANCELLED
Introduction to Fan Out Packaging
Course Leader: John Hunt, ASE Group
PDC 2:
System-in-Package (SiP) System Solutions Through Miniaturization
Course Leader: Mark Gerber, ASE Group
PDC 3:
Basics of Conventional and Advanced Chip Packaging
Course Leader: Syed Sajid Ahmad, CrossFire Tech
 
12:00pm-1:00pm
LUNCH
(Only provided for those attendees registered for BOTH morning and afternoon PDCs)
EARLY AFTERNOON COURSES:
1:00PM-3:00PM
PDC 4:
Development of Advanced Fan Out Technologies
Course Leader: John Hunt, ASE Group
PDC 5:
3D Package Assembly and Technology for Mobile Devices
Course Leader: Tom Dory, Fujifilm Electronic Materials
PDC 6:
Gold-Aluminum Intermetallics
Course Leader: Syed Sajid Ahmad, CrossFire Tech
PDC 7:
Fundamentals of 5G
Course Leader: Ivan Ndip, Fraunhofer IZM
3:00pm-3:30pmCOFFEE BREAK IN FOYER
LATE AFTERNOON COURSES:
3:30PM-5:30PM
PDC 8:
Advances in Fan-Out Wafer Level Packaging (FOWLP)
Course Leader: Beth Keser, Intel Corporation
PDC 9:
The Evolution of Flip Chip Package Technology
Course Leader: Mark Gerber, ASE Group
PDC 10:
Polymers in Wafer Level Packaging
Course Leader: Jeffrey Gotro, InnoCentrix, LLC
PDC 11:   CANCELLED
Advanced Assembly Processes of  Wafer Level Fan Out Packaging 
Course Leader: Tom Dory, Fujifilm Electronic Materials
5:30pm-7:00pmWELCOME RECEPTION
(All registered Conference attendees are invited to attend)

Thank you to our 2020 Premier Sponsors!
Platinum Sponsor:
Platinum Sponsor: ASE Group 
   

Gold Sponsors:

          

Silver Sponsors:

                               
 
  TUESDAY, MARCH 3, 2020                                                                                       Morning Technical Sessions
7:00am-
7:00pm
Registration
7:00am-
8:00am
Continental Breakfast Sponsored by:

                               
 
8:30am-
8:50am
 
**CONFERENCE NOW BEGINS AT 8:30**
OPENING COMMENTS
General Chair: Rama Puligadda, Brewer Science


Keynote Sessions Sponsored by:



Room 107-108
 KEYNOTE 1:     **MOVED TO 6:30-7:00PM TUESDAY EVENING**
HETEROGENEOUS INTEGRATION TECHNOLOGIES FOR MOORE'S LAW 2.0 AND BEYOND

This speech presents a vision and long-term semiconductor technology migration path to achieve two critical goals- extension of Moore’s Law and to enable energy-efficient AI compute. Holistic WLSI, a disruptive wafer-level heterogeneous integration technology platform as an example, can realize micro-system scaling in wafer form at conventional front-end stage as well as back-end stage to achieve the above-stated goals. 

Douglas Yu, Vice President R&D, TSMC
8:55am-
9:10am
UPDATES FROM IMAPS PRESIDENT
Rich Rice, Sr. VP, Marketing and Technology Promotion, ASE (US) Inc.
9:10am-
9:55am
KEYNOTE 2:
RF FRONT END PACKAGING CHALLENGES IN 5G

Mobile Technology in general and cell phones in particular have been a driving factor for electronic packaging innovations since the beginning and at the same time packaging innovations have been an enabler for more user-friendly form factors and / or increased functionality. The introduction and worldwide ramp of 5G marks a new turning point in this relationship as the capabilities of handsets are significantly improving and requirements for RF packaging are getting more demanding. The RF front end (RFFE) is a major contributor to these enhanced capabilities as it forms the link between the modem and the network.

5G presents additional challenges to the RF front end design when compared to the 3G / 4G transition. These challenges come from various aspects of 5G such as the increased bandwidth of the new sub 6 GHz frequency bands, the option to operate 4G and 5G in the sub 6 GHz frequency range at the same time, the introduction of mm wave frequencies to the RF front end and the generally stricter requirements on signal integrity.

While technical solutions for most of these challenges already exist in some form it becomes a challenge of its own to provide them in a package that is compatible with today's mobile phone designs.
                                        Dr. Christian Hoffmann, Principal Engineer, Qualcomm Germany RFFE GmbH

Christian Hoffmann is a member of the New Technology Business Development organization of the RFFE business unit and is responsible for technology pathfinding in the area of RF packaging. He joined Siemens Matsushita Components in Deutschlandsberg / Austria in 1998 as development engineer for RF ceramic materials and base station products before becoming head of technology development for the newly established LTCC technology in 2001. After 2006 he was responsible for all ceramic material research & development in Deutschlandsberg and when TDK acquired EPCOS in 2008 Christian Hoffmann became the 1st EPCOS engineer to work at the TDK R&D headquarter in Ichikawa / Japan. Returning to Germany in 2014 he started at the CTO Office of the SAW business group which after the acquisition by Qualcomm became the New Technology Business Development department of the RFFE BU. Christian Hoffmann is a member of the American Ceramic Society and IMAPS and helped to bring both societies together for a new conference series which would become CICMT. He served as technical co chair for CICMT and as general co chair of the 1st CICMT event outside of the US 2008 in Munich / Germany. Christian Hoffmann has a diploma in Physics and a doctor degree in Electrical Engineering from the University of Aachen / Germany.
9:55am-
10:00am
CONFERENCE LEADERSHIP RECOGNITION
General Chair: Rama Puligadda, Brewer Science
10:00am-
6:30pm
EXHIBITION OPEN
(Wasaja Ballroom)
10:00am-
10:30am
Break in the Exhibit Hall Sponsored by:
Corporate Sponsor: PacTech
 3D INTEGRATION Track
Room 107-108
FAN-OUT, WAFER LEVEL PACKAGING & FLIP CHIP Track
Room 104-106
ADVANCED & EMERGING MATERIALS for AUTOMOTIVE, 5G & NEXT GEN APPLICATIONS Track
Room 102-103
 TUESDAY MORNING 
SESSIONS
T-AM1:
APPLICATION & DESIGN
Chairs: Dongshun Bai, Brewer Science; Vik Chaudhry, Amkor Technology


 
 T-AM2:
CHALLENGES IN FAN-OUT WAFER LEVEL PACKAGING
Chairs: Beth Keser, Intel Corporation; Nokibul Islam, JCET Group

 
 T-AM3:
AUTOMOTIVE PACKAGING TRENDS
Chair: Prasad Dhond, Amkor Technology
10:30am- 
11:00am

 
**Presentation Cancelled**  
032
This is Not Your Father’s Semiconductor Packaging…An EDA Perspective
John Park, Cadence Design Systems
 042
Design Process & Methodology for Achieving High-Volume Production Quality for HDFO Packaging
Ruben Fuentes, Amkor Technology (Keith Felton, Mentor, a Siemens Business)
 064
Automotive Packaging Trends - Challenges and Solutions
Eungsan Cho, Infineon Technologies Americas Corp. (Thorsten Meyer)
11:00am-
11:30am
**Presentation Cancelled**
012
Silicon Capacitor Highly Integrated in Medical Systems Thanks to the Embedded Technology
Catherine Bunel, MURATA (Mickael Pommier)
 048
RF Analysis of Fan-Out Wafer Level Packaging Concepts with Integrated Antennas for 5G Applications
Ivan Ndip, Fraunhofer IZM (Marco Rossi, Tanja Braun, Thi Huyen Le, Abhijeet Kanitkar, Friedrich Müller, Marcel Wieland, Christian Goetze, Saquib Bin Halim, Jean Trewhella, Klaus Dieter Lang)
 041
Achieving Success in Automotive Leadframe Packages
John Nickelsen, Amkor Technology
11:30am-
12:00pm
 066
Samsung Foundry's 3D PKG Solution based on Cadence Design Flow
Max Min, Samsung Foundry US (SungWook Moon)
 060
Fan Out Wafer Level Package with Enhanced Product Reliability and Advanced Node Silicon Chip Package Integration
Gaurav Sharma, NXP Semiconductors (Nishant Lakhera, Craig Beddingfield, Mollie Benson, Andrew Mawer)
 062
Design and Process Considerations for Using Flip-chip Packaging Technology for the Automotive Market
Vinayak Pandey, JCET Group (Nokibul Islam)
12:00pm-
12:30pm
 058
Thermal Management Implications for Heterogeneous Integrated Packaging
Cameron Nelson, Amkor Technology
073 -- New Presentation
Trends in Fan-Out Wafer Level Processing: 600mm Panel Level for 6-Sided Die Protection M-Series
Jacinta Aman Lim, nepes corporation (Jay Kim, YM Park, Brett Dunlap)

 006 --  PRESENTATION CANCELED
Reliability Simulation with the Finite Element Analysis (FEA) of Redistribution Layer in Fan-out Wafer Level Packaging (FOWLP)
Yuji Okada, Asahi Kasei Corporation (Akira Fujii, Kenta Ono, Yoshiharu Kariya)
 052
Copper Wire Ready for Automotive AEC Requirements?
William Crockett, Tanaka Kikinzoku International (America)                        
12:30pm- 2:00pmLunch Sponsored By:

          


Sponsor - EMD Performance Materials
 
 
 
 TUESDAY, MARCH 3, 2020                                                                                    Afternoon Technical Sessions
  3D INTEGRATION Track
Room 107-108
 FAN-OUT, WAFER LEVEL PACKAGING & FLIP CHIP Track
Room 104-106
ADVANCED & EMERGING MATERIALS for AUTOMOTIVE, 5G & NEXT GEN APPLICATIONS Track
Room 102-103
TUESDAY AFTERNOON SESSIONS

T-PM1:
TECHNOLOGY - ORGANIC & SILICON BASED 3D
Chairs: Suresh Jayaraman, Amkor Technology; Stevan Hunter, ON Semiconductor; Marco Del Sarto, STMicroelectronics

T-PM2:
ADVANCES IN PROCESS, MATERIALS, AND EQUIPMENT FOR FAN-OUT WAFER LEVEL PACKAGING
Chairs: Curtis Zwenger, Amkor Technology; Farhad Kiaei, HD MicroSystems

T-PM3:
AUTOMOTIVE and 5G SIPs
Chairs: Tu-Anh Tran, NXP Semiconductors; Bora Baloglu, Amkor Technology

2:00pm-
2:30pm
016
An Embedded Planar-Foil Capacitor Material FPGA Interposer Aimed at Improving System Performance and Reduce Board Size for Space Based Electronics
Don Hunter, Jet Propulsion Laboratory (Gary Bolotin, Malcolm Lias, Ben Cheng)
043
Enabling Fine Line RDL and High Aspect Ratios for Cu Pillars for Heterogeneous Integration
Fabian Benthaus, Suss MicroTec (Yajun Gu, Habib Hichri, Markus Arendt)
036
The New Technology Solutions for Advanced SiP Devices
YongJai Seo, Amkor Technology
2:30pm-
3:00pm
021
PCB embedding of Magnetic Material for Inductor-based Applications
Gerald Weis, AT & S Austria Technologie & Systemtechnik Aktiengesellschaft
013
Improving WID and WIW Non-Uniformity in ECD Applications             
Charles Sharbono, Applied Materials
005
An Instrumented Getter for Hermetically Sealed Packages
Robert Dean, Auburn University (Michael Previti)

047 --  PRESENTATION CANCELED

Application of Vertically Aligned CNT Sheets to Die Attachment for Future Power Semiconductor Devices
Daiyu Kondo, Fujitsu Laboratories Ltd. (Shinichi Hirose, Koichi Suzuki, Masaaki Norimatsu, Yu Oyama, Shintaro Sato)
3:00pm-
3:30pm
056
Adaptive High Density RDL Technologies for Panel Level Packaging
Lars Boettcher, Fraunhofer IZM (S. Kosmider, F. Schein , R. Kahle, A. Ostmann)
001
Embedded Trace and RDL Copper Plating Process for Panel Level Packaging Applications
Kesheng Feng, MacDermid Alpha Electronics Solutions (Saminda Dharmarathna, William Bowerman, Jim Watkowski, Leslie Kim, Johnny Lee)
082
Enhancing the Punch MLF®/QFN Package for Improved Robustness in Automotive Applications
Marc Mangrum, Amkor Technology
3:30pm-
4:00pm
Break in the Exhibit Hall Sponsored by:
Break Sponsor: Quik-Pak
4:00pm-
4:30pm
007
Through Silicon Via Undercut Profile Optimisation for 3D Packaging Applications
Paul Gray, SPTS Technologies (Janet Hopkins, Huma Ashraf, Lijie Li)
054
Multipurpose Use of Laser-Sensitive Materials for Temporary Bonding and Debonding Applications in Wafer-Level Packaging
Luke Prenger, Brewer Science (Xiao Liu, Lisa Kirchner, Xavier Martinez, Samantha Oelklaus, Rama Puligadda)
002
Advanced Double Side SiP with Thermal Enhance Solutions for 5G Mobile Application
Mike Tsai, SPIL (Ryan Chiu, Eric He, J. Y. Chen, Frank Chu, Jensen Tsai, Yu-Po Wang, Shunyu Jian, Simon Chen)
4:30pm-
5:00pm
046
Thin Quad Die Package (QDP) Development
Shaun Bowers, Amkor Technology, Inc.
NEW PRESENTATION
3D Integration through wafer bonding for high density packaging (HDI)

Rafi Islam, Cactus Materials

053  -
PRESENTATION CANCELED
Latest Technology of Epoxy Molding Compound (EMC) for FO-WLP
Takeshi Mori, Sumitomo Bakelite Co.,Ltd.
030
A New Level of Connectivity- 5G Package Considerations
Mark Gerber, ASE US Inc.
5:00pm-
5:30pm
070
PCB Embedding Technology for 5G mmWave Applications
Stefan Kosmider, Fraunhofer IZM (Kavin Murugesan, Te Huyen Le, Uwe Maaß, Marco Rossi, Lars Boettcher)
057
Die Crack Prevention and Detection in Advanced Packaging
Woo Young Han, ONTO Innovation
050
3D Integrated Antennas for Millimeter-Wave and Terahertz Wireless Communication and Radar Sensing
Ivan Ndip, Fraunhofer IZM (Thi Huyen Le, Klaus-Dieter Lang)
5:30pm-
6:30pm
Exhibit Hall Reception Sponsored by:

Exhibit Reception Sponsor: Technic      Exhibit Reception Sponsor: Xperi
6:30pm-
8:00pm
EVENING KEYNOTE & PANEL DISCUSSION
Panel Session, Drinks & Food Sponsored by: 
Panel Session Sponsor: Evatec

Room 107-108
6:30pm-
7:00pm
KEYNOTE:
HETEROGENEOUS INTEGRATION TECHNOLOGIES FOR MOORE'S LAW 2.0 AND BEYOND

This speech presents a vision and long-term semiconductor technology migration path to achieve two critical goals- extension of Moore’s Law and to enable energy-efficient AI compute. Holistic WLSI, a disruptive wafer-level heterogeneous integration technology platform as an example, can realize micro-system scaling in wafer form at conventional front-end stage as well as back-end stage to achieve the above-stated goals.
 
Keynote: Douglas Yu, TSMCDouglas Yu, Vice President R&D, TSMC

Dr. Yu is a Vice President of TSMC R&D, responsible for the development of advanced Integrated Interconnect & Packaging technologies.  He has been in charge of on-chip interconnects (Cu/Low-K and Cu/ELK), and wafer-level system integration (WLSI including CoWoS®, InFO and SoICTM, etc.) technology developments.  These are the first technologies introduced to set new standards and start a new trend for semiconductor industry.

Doug worked with AT&T Bell Labs previously. He received his Ph.D. in Materials Engineering from Georgia Institute of Technology. Dr. Yu is an IEEE Fellow in recognition of his leadership in IC interconnect technology development.  He was awarded President Science Prize, among the most prestigious Taiwan science award. Doug has been granted 1000+ US patents.  He has over 150 technical publications with numerous plenary, keynote and invited speeches in leading international conferences, plus several semiconductor book chapters. 
7:00pm-
8:00pm

PANEL DISCUSSION:

High Performance Computing:  Are Chiplets the Answer?

 
Moderators:
Jan Vardaman, TechSearch International; Beth Keser, Intel Corporation
 
Panelists:

Robert Patti, NHanced Semiconductors, Inc.
Kevin Yee, Samsung
Paul Mescher, Microsoft
Jawad Nasrullah, zGlue
Ravi Mahajan, Intel Corp.

 

No longer can the industry count on monolithic integration to achieve the economic gains of the previous era.  New packaging solutions are being adopted to achieve the economic advantages that were previously met with silicon scaling.  The role of heterogeneous integration, especially chiplets, is pivotal in this new era.  TSMC indicates that the use of chiplets will be one of the most important developments for the next 10 to 20 years.  A chiplet is a functional circuit block and includes reusable IP blocks.  A chiplet can be created by partitioning a die into functions and is typically attached to a silicon interposer or organic substrate today, but new options are emerging such as advanced fan-out, RDL interposer, embedded bridges, and 3D packaging. This panel discussion provides insight into some of the applications driving the use of chiplets and explores challenges in bringing this into HVM.


Panel Session, Drinks & Food Sponsored by: 

Panel Session Sponsor: Evatec

Room 107-108

 

 
  WEDNESDAY, MARCH 4, 2020                                                        GBC Plenary Session
  
Welcome to the Global Business Council (GBC) Keynote & Plenary Session on
ELECTRONICS INDUSTRY TRANSITION

 
7:00am-
6:00pm
Registration
7:00am-
8:00am
Continental Breakfast Sponsored by:

                               
8:00am-
8:15am
GBC OPENING COMMENTS:
GBC Chairs: Lee Smith, Consultant; Rich Rice, ASE Group; Thomas Goodman, Izinus
 
Plenary Sessions Sponsored by:


Room 107-108
8:15am-
8:45am
Subramanian “Subu” S. Iyer, Distinguished Professor and Charles P. Reames Endowed Chair, UCLA
HETEROGENEOUS INTEGRATION, DIELETS AND CHIPLETS – WHY THE HYPE?
Looking at the news media and technical literature, one would think that the world has just discovered heterogeneous integration. In reality packaging has always been about heterogeneous integration. What is new is the scale of this integration in terms of connection pitches and the newer technologies that can presumably take this to the next level, including the fact that chiplets/dielets will be an increasingly important part of the ecosystem. This talk will explore these aspects and the implications on the eco-system and supply-chain in the area of high-performance computing, especially machine learning and AI, consumer electronics and medical electronics.

Subramanian S. Iyer (Subu) is Distinguished Professor and holds the Charles P. Reames Endowed Chair in the Electrical Engineering Department and a joint appointment in the Materials Science and Engineering Department at the University of California at Los Angeles. He is Director of the Center for Heterogeneous Integration and Performance Scaling (CHIPS). Prior to that he was an IBM Fellow. His key technical contributions have been the development of the world’s first SiGe base HBT, Salicide, electrical fuses, embedded DRAM and 45nm technology node used to make the first generation of truly low power portable devices as well as the first commercial interposer and 3D integrated products. He also was among the first to commercialize bonded SOI for CMOS applications through a start-up called SiBond LLC. More recently, he has been exploring new packaging paradigms and architectures that may enable including in-memory analog compute and medical engineering applications. He has published over 300 papers and holds over 70 patents. He has received several outstanding technical achievements and corporate awards at IBM. He is an IEEE Fellow, an APS Fellow and a Distinguished Lecturer of the IEEE EDS and EPS as well as the treasurer of EDS and a member of the Board of Governors of IEEE EPS. He is also a Fellow of the National Academy of Inventors. He is a Distinguished Alumnus of IIT Bombay and received the IEEE Daniel Noble Medal for emerging technologies in 2012.
8:45am-
9:15am
Rich Rice, Sr. VP, Marketing and Technology Promotion, ASE (US) Inc.
INTEGRATION TECHNOLOGIES TRANSFORMING THE WORLD 

The electronics industry is transforming our world, significantly driven by semiconductor innovation that is enabling life-changing applications from health to transportation, from virtual reality to AI. Advances in silicon integration technologies are proving truly revolutionary, where multiple die from multiple sources of varying functionality, are being combined to achieve unprecedented performance and operating characteristics. The packaging industry is at the forefront for the enablement of this integration. With a comprehensive tool box leveraging innovative technologies such as 2.5D & 3D die interconnection, high density fan-out, embedded devices, conformal and compartmental shielding, integrated antenna, and more, System-in-Package (SiP) portfolios are constantly being refined and enhanced to support growing demand for next generations of system integration.  During his talk, Yin Chang will describe the expanding application landscape, discuss integration technology innovation, and explore how SiP technologies are delivering on their promise of miniaturization, power efficiency, and highest performance yet.

Rich Rice currently serves as Senior Vice President of Marketing and Technology Promotion at ASE, with responsibilities within the North America region. Since joining ASE in 2003, Rich has also held positions overseeing Business Development, West Region and North American sales and applications engineering support.
 
Rich has gained over thirty-six years of experience within the semiconductor industry, having previously performed various engineering and business development roles both at Amkor Technology and National Semiconductor Corporation. He actively serves in advisory roles for the iMAPS Executive Council as President of the society, iMAPS Global Business Council, the ISS organizing committee for SEMI, the board of directors of a privately held technology company, as well as co-chair of the automotive TWG for the HIR (Heterogeneous Integration Roadmap) effort lead by Dr. Bill Chen and Dr. Bill Bottoms. Rich holds a BS degree in Agricultural Engineering from the University of Illinois. 
9:15am-
9:45am
E. Jan Vardaman, President and Founder, TechSearch International, Inc.
INTERCONNECT TRANSITIONS AND THE CHALLENGE AHEAD 

Wire bond still accounts for the majority of semiconductor package interconnect, but the strongest growth is in advanced packages such as flip chip and wafer level packages.  On the horizon is hybrid bonding or direct bond interconnect.  This presentation discusses interconnect transitions, including developments in existing interconnect methods such as wire bonding, tape automated bonding (TAB), and copper clip bonding.   The need for the infrastructure development to support a major change in interconnect technology is discussed.  The drivers and challenges for the new era in hybrid bonding are explored.

E. Jan Vardaman is president and founder of TechSearch International, Inc., which has provided market research and technology trend analysis in semiconductor packaging since 1987.  She is the co-author of How to Make IC Packages (by Nikkan Kogyo Shinbunsha), a columnist with Printed Circuit Design & Fab/Circuits Assembly, and the author of numerous publications on emerging trends in semiconductor packaging and assembly.  She served on the NSF-sponsored World Technology Evaluation Center (WTEC) study team involved in investigating electronics manufacturing in Asia and on the U.S. mission to study manufacturing in China.   She is a senior member of IEEE EPS and is an IEEE EPS Distinguished Lecturer.  She is a member of SEMI, IMAPS, and SMTA.  She received the IMAPS GBC Partnership award in 2012, the Daniel C. Hughes, Jr. Memorial Award in 2018, and the Sidney J. Stein International Award in 2019.  She is an IMAPS Fellow.  Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium.
9:45am-
10:45am
Break in the Exhibit Hall Sponsored by:
10:45am-
11:15am
Vaibhav Trivedi, Sr. Technology Market Analyst, Yole Development  
ADVANCED PACKAGING LEAD SEMICONDUCTOR TRANSITION INTO THE NEXT DECADE
Over last decade, advanced packaging such as fan-out wafer or panel level, side molded WLCSP, and SiP have changed the landscape of the semiconductor supply chain driven by mobile applications.  This presentation will explore advancements in advanced packaging technologies in terms of scaling, heterogenous integration, and advanced packaging process development over last ten years and provide insight on how this will shape the next decade.

A deep dive into the trends and advancements for fan-out wafer and panel level packaging will be explored as these technologies are impacting the overall packaging supply chain including: IDM, Foundry, OSAT and substrate supply. Fan-out packaging will be addressed as a vehicle and enabler supporting industry transition with its various configurations from package/process standpoint.


Vaibhav Trivedi is a Senior Technology & Market analyst at Yole Développement (Yole) working with the Semiconductor & Software division. Based in the US, he is a member of Yole’s advanced packaging team and contributes to analysis of ever-changing advanced packaging technologies. Vaibhav has 17+  years of field experience in semiconductor processing and semiconductor supply chain, specifically on memory and thermal component sourcing and advanced packaging such as SiP and WLP. Vaibhav has held multiple technical and commercial lead roles at various semiconductor corporations prior to joining Yole. Vaibhav holds a Bachelor of Science in Chemical Engineering, and Master of Science of Material Science from University of Florida in addition to an MBA from Arizona State.
11:15am-
11:45am
Andrea Lati, Vice President, Market Research, VLSI Research
RECOVERY: WHEN DID IT START...WHAT DROVE IT...HOW LONG WILL IT LAST

2019 was a tough year for the industry with both IC and Equipment sales falling by double digits. Unlike the previous cycles, the equipment market fared better than semiconductors in 2019, powering out of downturn territory in the second half of the year. So what will 2020 bring for the industry? Will the equipment market continue to lead semiconductors and maintain the momentum?

Some of the questions to be addressed in the presentation include:
  • What is the growth range that can be expected?
  • How will this growth be achieved?
  • What are the key drivers and pivot points?
  • How are current trends and issues likely to unfold in the coming year?
  • Where will the best markets and opportunities be?

Andrea Lati is the Vice President, Market Research at VLSI Research Inc. Since joining VLSI Research in 2001, Andrea has been focusing on managing and developing forecasting models as well as performing market analysis and research on electronics, semiconductor, and equipment markets. In addition, Andrea has performed many custom studies for various clients and is a co-author of The Chip Insider ®.  He earned his bachelor’s degree in Mathematics and Economics from the University of California Santa Barbara.
11:45am-
12:00pm
GBC CLOSING REMARKS
12:00pm-
1:30pm
Lunch Break in the Exhibit Hall Sponsored by: (Food served 12:00pm -1:00pm)

Lunch Sponsored By:

          



 
 
 WEDNESDAY, MARCH 4, 2020                                                                             Afternoon Technical Sessions
  3D INTEGRATION Track
Room 107-108
 FAN-OUT, WAFER LEVEL PACKAGING & FLIP CHIP Track
Room 104-106
ADVANCED & EMERGING MATERIALS for AUTOMOTIVE, 5G & NEXT GEN APPLICATIONS Track
Room 102-103

WEDNESDAY
AFTERNOON
SESSIONS:

W-PM1:

TECHNOLOGY - 3D SILICON & GLASS
Chairs: Rafiqul Islam, Cactus Materials; Lars Böttcher, Fraunhofer IZM

W-PM2:

PACKAGING ADVANCES IN HIGH PERFORMANCE COMPUTE
Chairs: Scott Hayes, NXP; Jae Kyu Cho, Global Foundries

W-PM3:

NEXT GEN APPLICATION SOLUTIONS
Chairs: Trevor Yancey, TechSearch International; Jon Aday, Illumina

1:30pm
2:00pm
059
Heterogeneous Packaging, Chiplets and the Quest for Higher Performance
Mike Kelly, Amkor Technology (Dave Hiner,   Curtis Zwenger, George Scott, Ron Huemoeller)
014
Fluxless Thermocompression Flip Chip Bonding Via In-Situ Oxide Reduction Bonding
Bob Chylak, Kulicke and Soffa Industries (Tom Colosimo, Adeel Bajwa, Horst Clauberg)
**PRESENTATION CANCELLED**
037
Chip-to-Chip Integration for High Bandwidth Memory Processor Interface
Andy Heinig, Fraunhofer IIS/EAS (Fabian Hopsch)
2:00pm-
2:30pm
076
In-process Warpage Prediction and Optimization for Heterogeneously Integrated Packages Using a Novel Thermo-mechanical Modeling Scheme 
Priyal Shah, Advanced Micro Devices, Inc. (Milind Bhagavat)
010
10 micron Pitch Wiring and Bump on Substrate Formed by Imprinting Technology to Apply Low Temperature Flip Chip Bonding
Hiroshi Komatsu, CONNECTEC JAPAN Corporation (Nozomi Shimoishizaka, CONNECTEC JAPAN Corporation; Toshihiro Yamada, Industrial Research Institute of Niigata Prefecture)
**PRESENTATION CANCELLED**
011
Low Cost EMI Shielding Using Silver Particles and CNTs
Byounggug Min, Samsung Electronics (Min woo Song, Jongkak Jang, SangHo An)
2:30pm-
3:00pm
NEW PRESENTATION
Radiation hardened low gain avalanche detector by wafer-to-wafer bonding

Rafi Islam, Cactus Materials

071 -- 
PRESENTATION CANCELED
3D Packaging. MEMS and Sensor Point of View
Marco Del Sarto, STMicroelectronics
028
Applications of Novel High-speed In-line Automatic X-ray Inspection in High-volume Manufacturing
Frank Chen, SVXR, Inc.
038
Coating Adhesion Testing for Improved RF
Thomas Monaghan, Knowles Corp
3:00pm
4:00pm
Break in the Exhibit Hall Sponsored by:
Break Sponsor: Spectrum Semiconductor Materials
4:00pm-
4:30pm
069
Glass Interposers Using Cu-plated Through Glass Vias (TGVs)
Charles Woychik, i3 Microsystems, Inc. (Justin Borski, Robert Nead)
004
Solution for Accelerator Wall of HPC with HBM Integrated Packages
JinWei You, Siliconware Precision Industries Co. Ltd (Yu-Po Wang, Cheng Kai Chang, Teny Shih, Nicholas Kao)
008
Prototyping IoT Modules Assembled by Additive Manufacturing
Steve Watt, Yoko Fujita, Zuken Inc.
4:30pm-
5:00pm
074
Leading Edge Glass Interposer for High frequency application
Satoru Kuramochi, Dai Nippon Printing co Ltd (Masaya Tanaka)
039
Decision System In Package in IoT/5G Application
Tuan Hoang, Zuken Inc.
019
Advancements and Integration of Thin Glass Solutions
Aric Shorey, Mosaic Microsystems (Shelby Nelson, David Levy, Paul Ballentine)
5:00pm-
5:30pm
079
Cu Interconnect Scaling with Hybrid Bonding for 2.5 and 3D Integration
Laura Mirkarimi, Xperi (Thomas Workman, Gill Fountain, Guilian Gao, Jeremy Theil, Gabe Guevara, Bongsub Lee, Dominik Suwito, Pawel Mrozek)
045
Backside Metallization for Low Cost High Thermal Package
Nokibul Islam, JCET Group (Chris Scanlan, WQ Jin, SY Chai)
023
Micro-Features in Glass using Laser Induced Deep Etching for Device  Packaging
Jean-Pol Delrue, LPKF Laser & Electronics (Rafael Santos, Norbert Ambrosius, Roman Ostholt, Stephan Schmidt)
  POSTER SESSION & HAPPY HOUR 
Outside on the patio overlooking the desert 5:30pm - 6:30pm

(Poster Session Setup - 4:00pm - 5:25pm)
(additional abstracts in regular session will also participate)

Poster Session & Happy Hour (5:30pm-6:30pm) Sponsored by:
 
Poster Session Sponsor: MacDermid AlphaPoster Session Sposnor: ECI Technology


Session Chair: Syed Sajid Ahmad
 

005
An Instrumented Getter for Hermetically Sealed Packages
Robert Dean, Auburn University (Michael Previti)

 067
Thermal Interface Material Dispense in Power Module and 5G Device Package Applications
Hanzhuang Liang, Nordson Asymtek

 018

Novel Low Temperature Curable Photo-Patternable Low Dk/Df for Wafer Level Packaging (WLP)
Katie Han, Kayaku Advanced Materials/Nippon Kayaku (Yasumas Akatsuka, Jenna Cordero, Shinya Inagaki, Daniel Nawrocki)

**CANCELLED**
072

Early Detection of Photoresist Contamination in Plating Baths - Inline Process Control Methodology
I. Popova, Ancosys Inc. (N. Schroeder, R. Dickman, R. Suter, J. Stahl)

 024
Dual-cure Sealing of Assemblies for Automotive Manufacturing        
John Moore Daetec LLC (R Gorski, N Kreiner, C Padfield, H Rehman, A Riekenbrauck, C Davis, T “TJ” Fagòt, A Gray)
**ALSO PRESENTED IN SESSION T-AM2**
073

Trends in Fan-Out Wafer Level Processing: 600mm Panel Level for 6-Sided Die Protection M-Series
Jacinta Aman Lim, nepes corporation (Jay Kim, YM Park, Brett Dunlap)
 031
Damping Materials for Shock Performance of Micromachined Vibration Isolators
Brent Bottenfield, Auburn University (Artie Bond, Mike Kranz, Brian English, Robert Dean, Mark Adams)
**CANCELLED**
075
Contamination Troubleshooting for Microelectronics Packaging 
Victor K.F. Chia, Air Liquide Electronics - Balazs NanoAnalysis
033
Assembly of Intradermic, Micro, Silicon Needle Using Standard Die Bonding Equipment
Jonathan Abdilla, BESI Austria GmbH (Zlatko Hajdarevic, Hannes Klingler, Lars Zondervan)
**CANCELLED**
077
Low Dielectric Loss Polyimide B-stage Sheet 
Masao Tomikawa, Toray Industries Inc. (Akira Shimada, Hitoshi Araki)

040
Thermal Cycling of Aerosol Jet(R) Printed Silver Interconnects
Kurt Christneson, Optomec (Patrick Welch, Shaun Bowers, Knowlton Olmstead)

078
Acceleration Factors and Life Predictions
Chris South, Ansys - DfR Solutions
063

New Technology Paths for Next Generation Packaging Using Advanced Innovative Laser Assisted 3.5D and SB2-WB Assembly Processes
Thomas Oppert, PacTech - Packaging Technologies GmbH (Matthias Fettke, Andrej Kolbasow, Thorsten Teutsch)

080
Carbon Nanofiber MIM Capacitors with Ultra-high Capacitance Densities, Low ESR and Large Operating Temperature Range
Vincent Desmaris, Smoltek AB (Sascha Krause, Rickard Andersson, Maria Bylund, Amin Saleem, Victor Marknas, Shafiq Kabir)

065
Computational Simulation of the Molecular Structure and Properties of MPS and SH110 in TSVs Copper Filling
Yuping Le, Central South University (Fuliang Wang)

081
Dynamic Maskless Aligner lithography: Flexibility for Packaging Applications
Philip Paul, Heidelberg Instruments Mikrotechnik GmbH
NEW
Manufacturing Technology Solution as Heterogeneous Integration for Future In-memory Computing
Yasuhiro Morikawa, ULVAC
**ALSO PRESENTED IN SESSION TH-AM3**
026
Online Monitoring of Panel Level Packaging Process Solutions
Michael Pavlov, ECI Technology (Karsten Andrae, William Finck, Jingjing Wang, Eugene Shalyt, Paul Okagbare, Vishal Parekh, Michael
MacEwan)
3DInCites
2020 3D InCites "Bonus Happy Hour" & Awards Ceremony

6:30pm-7:30pm

Immediately Following the Poster Session - Outside On Patio Overlooking Desert
 
 Post- Conference Presentations DOWNLOAD:
AVAILABLE 2 WEEKS AFTER CONFERNCE 
All full conference attendees & exhibitors will be emailed a link to download all of the technical presentation from Device Packaging 2020

Speakers – slides left on the session laptops will be used. Or you MUST send updated file to bschieman@imaps.org before the end of the conference.
 
THURSDAY, MARCH 5, 2020                                                                                       Morning Technical Sessions
7:00am-
11:30am
Registration
7:00am-
8:00am 
Continental Breakfast Sponsored by:

                               
7:55am-8:00am 
OPENING COMMENTS
General Chairs: Rama Puligadda, Brewer Science; Eric Huenger, DuPont Electronic & Imaging 


Keynote Sessions Sponsored by:


Room 107-108
8:00am-
8:45am

 
KEYNOTE 3:
INTEGRATED WAFER LEVEL PACKAGING TECHNOLOGIES FOR HIGH-PERFORMANCE COMPUTING SYSTEMS: CHALLENGES AND OPPORTUNITIES

Higher computing power and memory bandwidth are the major requirements of Al and 5G for GPU, accelerators and network devices. These demands lead to the adoption of the advanced packaging technologies to increase bandwidth density and to improve electrical performance with shorter interconnection length. For consumer application, panel level fan-out technologies are being used for consumer and mobile devices due to smaller form factors and higher electrical/thermal performances. Also, 3D TSV technologies provide high bandwidth density within a limited footprint. For network applications, 2.5D and 3D technologies are employed for cloud and artificial intelligence (AI). High-performance chip size continues to increase up to one reticle size and the cost of the leading-edge silicon node is recently soaring. So various chiplet packaging solutions, such as 2D, 2.5D and 3D are necessary to develop with the fine pitch bonding process and fine pitch interconnection evolutions. 

In this presentation, the above mentioned integrated wafer level packaging solutions are to be introduced and discussed in terms of challenges and opportunities for emerging high-end computing platforms. Furthermore, a high-performance 3D SiP system is introduced for signal/power efficiency and the extension of the fanout package for network/server application. 
 Keynote Speaker - Max MinMax Min, Samsung & Seung Wook Yoon, Corporate VP,  Samsung Electronics
Dr. Max Min is a Director from Samsung Foundry in San Jose. He has been working on Package and Signal and Power Integrity for 10 years. He was with R&D and Sales and is now with Marketing in Samsung Foundry. He received his Ph.D. degree in Electrical and Computer Engineering from Georgia Institute of Technology in 2004.
8:45am-
9:30am
KEYNOTE 4:
GET MOoRE OUT OF THE PACKAGE

The expectation of what progress must be achieved node-to-node in semiconductor scaling is quite clear: follow Moore’s Law. However, this alone will not suffice in enabling the next generation products our industry demands. Products are not simply isolated chips: chips need to integrate into a complex system of components. Package Integration is the main enabler to more functionality, more data, and higher speed at a product level. This presentation will investigate what it is we need to get out of the package in order to continue supporting solutions for next generation products. 
 Keynote: Wolfgang SauterDr. Wolfgang Sauter, Customer Engineering Solutions – Packaging, Marvell Semiconductor

Wolfgang Sauter is a Principal Engineer at Marvell's newly acquired ASIC Business Unit. He works on advanced package solutions and chip interface definition for all ASIC products that require integration of multiple active components. Before he started at Marvell Semiconductor, Wolfgang worked as a Packaging Engineer at IBM, and as a Customer Product Solutions Architect at Globalfoundries and at Avera Semi. Wolfgang has authored more than 30 industry papers and publications, and holds more than 120 patents.
9:30am-
9:45am
Break in the Foyer
 3D INTEGRATION Track
Room 107-108
FAN-OUT, WAFER LEVEL PACKAGING & FLIP CHIP Track
Room 104-106
ADVANCED PACKAGING & EMERGING MATERIALS for AUTOMOTIVE, 5G & NEXT GEN APPLICATIONS Track
Room 102-103
 THURSDAY
MORNING 
SESSIONS
 TH-AM1:
BONDING & METROLOGY
Chairs: Mike Kelly, Amkor Technology; Steffen Kroehnert, ESPAT-Consulting
 TH-AM2:
NOVEL CONCEPTS IN FAN-OUT & WAFER LEVEL PACKAGING
Chairs: Chris Scanlan, JCET Group; Trevor Yancey, TechSearch
 TH-AM3:
NEXT GEN APPLICATIONS
Chairs:  YongJai So, Amkor Technology; Tu-Anh Tran, NXP Semiconductors

 
9:45am-
10:15am
044
Paths towards Ultra High-Density Interconnect 3D Systems: Contribution of Wafer Geometry for Achieving sub 200nm Wafer-To-Wafer Bonding Overlay
Serena Iacovo, IMEC (Joeri De Vos, Alain Phommahaxay, Andy Miller, Eric Beyne, Thomas Uhrmann, Andreas Fehkuhrer)
 022
Polymer Enabled Ultra-thin Package Solutions for Heterogeneous, Package-in-package and Embedded ICs
Doug Hackler, American Semiconductor (Chris Milasincic, HD MicroSystems; Ed Prack, MASIP LLC)
 009
High Density Integrated Stack Capacitor (ISC) for Advanced Package Solutions
Max Min, Jaejune Jang, Samsung Foundry (Sugmin Hong, Jaeyup Chung, Yoojeong Jeong, Sunwoo Park, Jihyung Kim)
10:15am-
10:45am
 051
Collective D2W Hybrid Bonding for 3D SIC and Heterogeneous Integration
Thomas Uhrmann, EV Group (J. Burggraf, M. Pires)
 025
Heterogeneous System-in-Package (HSIP) Using Fan-Out Wafer-Level Packaging (FOWLP)
Charles Woychik, i3 Microsystems, Inc. (Justin Borski, Robert Nead)
 015
Development of Additive Technology for Advanced Packaging
Jason Rouse, Sekisui Products LLC (Takanori Inoue, Taichi Hamada, Yusuke Fujita, Yoshifumi Sugisawa, Mitsuru Tanikawa, Takashi Watanabe)
10:45am-
11:15am
 055
A Novel Permanent Bonding Material
Reihaneh Sejoubsari, Brewer Science (Xiao Liu, Trevor Stanley)
 035
Design Rule Study of Low Pressure Compression Molding Process on Polymer Cavity Packages
Nao Honda, Nippon Kayaku Co., Ltd.
 017
Autocatalytic Tin -  How to Overcome Process Limitations to Introduce a New Solution for Thick Tin Plating
Sandra Nelle, Atotech Deutschland GmbH (B. Schafsteller, K. Tuna, G. Ramos)
11:15am-
11:45am
 034
Improved Optical Profiler Metrology for Advanced Packaging
Samuel Lesko, Bruker - Nano Surfaces
 049
Glass based Panel Fanout Packaging for High-Frequency Applications
Siddharth Ravichandran, Georgia Institute of Technology (Atom Watanabe, Nobuo Ogura, Rao Tummala, Madhavan Swaminathan)
 026
Online Monitoring of Panel Level Packaging Process Solutions
Michael Pavlov, ECI Technology (Karsten Andrae, William Finck, Jingjing Wang, Eugene Shalyt, Paul Okagbare, Vishal Parekh, Michael
MacEwan)
11:45amCONFERENCE ENDS BY 11:45AM
FOUNDATION GOLF OUTING AT 1:30PM at WeKoPa Golf Course