Device Packaging 2020 PDCs

Professional Development Course Details

Register by February 3rd and save up to $100.


What are PDCs?

Professional Development Courses are supplemental two-hour classroom-style tutorials with a narrow educational focus taught by the best in the industry. The topics offered at DPC 2020 are designed to help attendees broaden their device packaging scope of knowledge.


Device Packaging 2020 Course Offerings

The 2020 PDC courses are offered on Monday, March 4th, preceding the technical conference. Attendees must register for each course as an add-on to their overall DPC 2020 conference registration. Attendees may select up to one course in each time slot.

  • Morning PDCs will run from 10:00am until 12:00 noon. 
  • Early afternoon PDCs will be held from 1:00pm until 3:00pm
  • Late afternoon PDCs will be held from 3:30pm until 5:30pm.


Course Fees and Inclusions

Course Fees: $325 per course if purchased before February 3rd | $425 per course if purchased after February 3rd
Fees include access to the 2-hour course led by reputable industry leaders and one hard copy of the course notes* designed by the instructor.
Register for an AM and a PM course and enjoy a boxed lunch.

*Additional hard copies of the course materials can be purchased for $425 each pending availability after the conclusion of the course. Electronic copies of course materials are not provided.

How to Register

Click here to begin the easy online registration process.

  1. Log into your member account or create a guest* account.
    *Remember! Member, Nonmember, Speaker, Chair, Chapter Officer, and Student event registrations include a one-year IMAPS membership. Make sure to populate your account thoroughly. Guest accounts will be converted to member accounts within 30 days of your event registration.
  2. Select the International Conference on Device Packaging event. 
  3. Select your overall conference registration type (Member, Nonmember, Speaker, Chair, Student).
    Only planning to attend a PDC? Select "PDC Only" as your registration type. 
  4. Choose your course(s) selection in the time slot drop-down boxes. Select up to one course per time slot.
  5. Check out. You will receive a confirmation email detailing your registration. 
If you need to add or change course selection(s) after completing a registration, please contact Shelby Moirano at 

Course Descriptions

There are several factors driving packaging evolution in the electronics industry today.  Mobile devices, along with the rise of the Internet of Things has driven the need for a continual reduction in the thickness and volume of semiconductor packaging.  And, as the wafer node advancement has slowed, the value of heterogenous integration of multiple active and passive devices into more complex packaging has become apparent.  What is needed now is the synergy of the reduction in size while at the same time the increase in complexity of new packaging technologies.

We will review how the integration of new wafer level processes and structures, substrate evolution and Flip Chip packaging have come together into what is being called Fan Out Packaging.  These packages are for both low density and high density, both Mobile and server applications. They have higher levels of Homogeneous and Heterogeneous integration and sophistication than has ever been possible in the past.  A basic description of the concept of Fan Out, a history of its evolution, structures and processes, and market trends will be included in this course.


This PDC course will introduce the package platform SiP (System-in-Package) and how some companies are diversifying from SOC (System-on-a-Chip) to leverage heterogeneous silicon integration and package miniaturization to enable system level solutions. A short market perspective will be reviewed as well as how industry segments are leveraging SiP and how the OEM market is evolving and creating system level ecosystems to enabling content revenue- a key area of IOT. SiP general process flow details will be covered as well as key process considerations for yield improvements. In addition, a brief overview of some of the tools that may be leveraged to help miniaturize module solutions and improve performance. This class will also introduce several variations of the SIP platform using Fan-Out Wafer Level packaging and new embedded substrate technologies are also emerging as powerful future platforms to enable lower power and higher performance devices using solderless interconnects.


The course presents manufacturing, materials, quality and reliability info in terms understandable to engineering and non-engineering personnel. Packaging characteristics and drivers will be outlined. Types of packages and critical differences among them and their applications will be discussed. The course will look at the design selection to meet use and application environments. Step-by step manufacturing flow for plastic packages will be presented as an example to understand the complexity of processes, materials and equipment involved in their manufacture. Advanced packaging will be introduced. Materials selection with respect to application environments will be discussed. Quality and reliability issues related to chip packaging and assembly and their solution will be outlined.


Fan Out technology has evolved as an alternative package to meet the need for miniaturization of electronics, while also providing improved electrical interconnectivity.  Until around 2016, Fan Out was considered primarily a solution for low density packaging requirements.

The wide use of mobile and many IOT devices coming into use has driven the need for increased capability of data centers.  Fan Out technology is now in production for many of these applications.  It also enables the heterogeneous integration of die and memory with improved electrical performance and lower cost than traditional 2.5 packaging for these data center requirements.

We will review how the integration of wafer level processing technologies; substrate evolution and Flip Chip packaging structures have come together into recent advances in both low density and high-density Fan Out packaging. These packages are for automotive, IoT, advanced mobile and server applications. They can have higher levels of integration and sophistication than has ever been possible in the past.  A brief overview of the concept of Fan Out packaging and history of its evolution, and recent Fan Out developments to meet both low- and high-end applications will be included in this course.


This PDC provides details on current and future assembly 3D packaging processes and technologies. The 3D IC and wafer-level packaging area is forecasted to grow to over $2.5 billion by 2016 driven by mobile devices including phone and tablet computers. Advanced packaging requirements require the evolution of back end manufacturing to become more process control driven. The 3D stacked die TSV packaging has advantages, but only in some market segments. In the cell phone market, stacking chips helps to minimize some of the interconnect issues between the logic and the memory chips. Wire bonding remains a key assembly method for 3D memory packages. This workshop will cover 3D and 2.5D (interposer) designs, 3D assembly flow, known good die, KGD, concerns, 3D package testing issues, supply line logistics, thermal management, logic bump out designs, wafer thinning and handling (thermal & laser debonding and residue removal) and interposers with microfluidics cooling built-in. The objective of this workshop is to provide the students with an overview of the technologies, materials, and processes involved in the latest 3D and 2.5D assembly processes.


Gold-aluminum wire bonding as an interconnection medium between the chip and the substrate or the printed circuit board has been an integral part of semiconductor packaging for decades. Since the introduction of plastic packaging, it stubbornly refuses to be replaced despite its inherent weaknesses. Occurrence of purple plague at the Au-Al interface has been a reliability concern since the introduction of Au-Al wire bonding. Efforts to understand and circumvent purple plague have as long a history as the Au-Al bond itself. Review historical timeline of the research in this area. Summarize and present pertinent results. Observation and measurement methods. Impact and remediation.


Basic concepts required for thorough understanding of 5G will first be explained. This will be followed by a presentation of challenges in the development of 5G mmWave systems, and possible solutions. The roles and requirements of electronic packaging in 5G will be illustrated. Furthermore, examples of packaging and RF system-integration platforms for the development of 5G mmWave modules and systems will be extensively discussed. Techniques for accurate RF measurement and characterization of 5G packaging materials will also be illustrated. Finally, basic antenna-in-package design considerations and techniques for 5G mmWave applications will be given.

Course Outline:

1) 5G cell structure and deployment timeline worldwide

2) Basics of MIMO, massive MIMO and beamforming for 5G

3) Challenges in the development of 5G mmWave systems, and possible solutions

4) Roles and requirements of electronic packaging in 5G mmWave

5) Examples of packaging and RF system-integration platforms for 5G mmWave applications

6) Illustration of techniques for RF measurement & characterization of 5G packaging materials

7) Basic antenna-in-package design considerations and techniques for 5G mmWave 


Fan-out wafer level packaging (FO-WLP) technologies have been developed across the industry over the past 15 years and have been in high volume manufacturing for over 10 years. FO-WLP has matured enough that it has come to a crossroads where it has the potential to change the electronic packaging industry by eliminating wirebond and bump interconnections, substrates, leadframes, and the traditional flip chip or wirebond chip attach and underfill assembly technologies across multiple applications. This course will cover the advantages of FO-WLP, potential application spaces, advanced package structures available in the industry, technology roadmaps, and benchmarking. The challenges of moving from 300mm FO-WLP to panel will also be discussed.


This PDC course will provide a historical overview and background on the evolution of flip chip packaging as well as short market perspective on this platform. Mobile, Infrastructure, Automotive, High Reliability, Medical and High-Performance Network and Computing all rely on Flip Chip technology to enable their silicon solutions.  Although the use of new technologies such as Fan-Out hold promise for certain applications, flip chip advancements continue to challenge many new technology competitors from a price and reliability perspective and may end up driving hybrid approaches.  Interconnect structure, process flows, materials and package integration process methods for evolving Flip Chip applications will be discussed in detail. Understanding the trade-offs between the different bump structures and package platforms is key in determining the silicon device layout and the type of design rules that can be leveraged for new products. As part of this course, the assembly process details will be discussed and will include Mass Reflow, Thermo-Compression Non-Conductive Paste (TCNCP) bonding and Laser Assisted Bonding. Reliability aspects such as IMC formations and ways to address will also be covered as a key consideration for Interconnect decisions.


The course will provide an overview of polymers used in wafer level packaging and the important structure-property-process-performance relationships for polymers used in wafer level packaging.  The main learning objectives will be: 1) gain insights on how polymers are used in Fan Out Wafer Level Packaging, specifically mold compounds and polymer redistribution layers (RDL) 2) learn the key polymer and processes challenges in Fan Out Wafer Level Packaging including panel level processing, and 3) understand the types of polymers used in wafer level packages, including pre-applied and wafer applied underfills. We will cover in more depth the chemistries, material properties, process considerations for polymers used in wafer level packaging.  The course has been completely updated to include a detailed discussion of the polymers and polymer-related processing for Fan-Out Wafer Level packaging (such as chip first and chip last process flows).

This PDC provides focuses on current and future assembly processes and technologies used in fan out package assembly. The objective of this PDC is to provide the students with an overview of the technologies, materials, and processes involved in the latest fan out package assembly processes.

Currently there are several choices for package assembly using fan out wafer level packages (FOWLPs).  The original fan-out package; the embedded wafer-level ball-grid array (eWLB) continues to be popular. At the low cost end are low density fan out packages with <500 IOs with >8 micron L/S. At the high cost end are stacked die packages with >500 IOs and < 8 micron L/S.  Multiple die can now be included in a fan out package incorporating stacked die connected using Through Silicon Vias (TSVs).

The fan out chip scale package, FOCSP, will be used as current state of the art example in the workshop. The package end user, designer and sub-cons must compare all package options on the basis of functional attributes including form factor, I/O density, performance & cost to select appropriate package from the many fan out options available.