Device Packaging 2020 PDCs
Professional Development Course Details
What are PDCs?
Device Packaging 2020 Course Offerings
- Morning PDCs will run from 10:00am until 12:00 noon.
- Early afternoon PDCs will be held from 1:00pm until 3:00pm.
- Late afternoon PDCs will be held from 3:30pm until 5:30pm.
Course Fees and Inclusions
Fees include access to the 2-hour course led by reputable industry leaders and one hard copy of the course notes* designed by the instructor.
Register for an AM and a PM course and enjoy a boxed lunch.
*Additional hard copies of the course materials can be purchased for $425 each pending availability after the conclusion of the course. Electronic copies of course materials are not provided.
How to Register
- Log into your member account or create a guest* account.
*Remember! Member, Nonmember, Speaker, Chair, Chapter Officer, and Student event registrations include a one-year IMAPS membership. Make sure to populate your account thoroughly. Guest accounts will be converted to member accounts within 30 days of your event registration.
- Select the International Conference on Device Packaging event.
- Select your overall conference registration type (Member, Nonmember, Speaker, Chair, Student).
Only planning to attend a PDC? Select "PDC Only" as your registration type.
- Choose your course(s) selection in the time slot drop-down boxes. Select up to one course per time slot.
- Check out. You will receive a confirmation email detailing your registration.
There are several factors driving packaging evolution in the electronics industry today. Mobile devices, along with the rise of the Internet of Things has driven the need for a continual reduction in the thickness and volume of semiconductor packaging. And, as the wafer node advancement has slowed, the value of heterogenous integration of multiple active and passive devices into more complex packaging has become apparent. What is needed now is the synergy of the reduction in size while at the same time the increase in complexity of new packaging technologies.
We will review how the integration of new wafer level processes and structures, substrate evolution and Flip Chip packaging have come together into what is being called Fan Out Packaging. These packages are for both low density and high density, both Mobile and server applications. They have higher levels of Homogeneous and Heterogeneous integration and sophistication than has ever been possible in the past. A basic description of the concept of Fan Out, a history of its evolution, structures and processes, and market trends will be included in this course.
System-in-Package (SiP) System Solutions Through Miniaturization
Course Leader: Mark Gerber, ASE Group
Basics of Conventional and Advanced Chip Packaging
Course Leader: Syed Sajid Ahmad, CrossFire Tech
Fan Out technology has evolved as an alternative package to meet the need for miniaturization of electronics, while also providing improved electrical interconnectivity. Until around 2016, Fan Out was considered primarily a solution for low density packaging requirements.
The wide use of mobile and many IOT devices coming into use has driven the need for increased capability of data centers. Fan Out technology is now in production for many of these applications. It also enables the heterogeneous integration of die and memory with improved electrical performance and lower cost than traditional 2.5 packaging for these data center requirements.
We will review how the integration of wafer level processing technologies; substrate evolution and Flip Chip packaging structures have come together into recent advances in both low density and high-density Fan Out packaging. These packages are for automotive, IoT, advanced mobile and server applications. They can have higher levels of integration and sophistication than has ever been possible in the past. A brief overview of the concept of Fan Out packaging and history of its evolution, and recent Fan Out developments to meet both low- and high-end applications will be included in this course.
3D Package Assembly and Technology for Mobile Devices
Course Leader: Tom Dory, Fujifilm Electronic Materials
Basic concepts required for thorough understanding of 5G will first be explained. This will be followed by a presentation of challenges in the development of 5G mmWave systems, and possible solutions. The roles and requirements of electronic packaging in 5G will be illustrated. Furthermore, examples of packaging and RF system-integration platforms for the development of 5G mmWave modules and systems will be extensively discussed. Techniques for accurate RF measurement and characterization of 5G packaging materials will also be illustrated. Finally, basic antenna-in-package design considerations and techniques for 5G mmWave applications will be given.
1) 5G cell structure and deployment timeline worldwide
2) Basics of MIMO, massive MIMO and beamforming for 5G
3) Challenges in the development of 5G mmWave systems, and possible solutions
4) Roles and requirements of electronic packaging in 5G mmWave
5) Examples of packaging and RF system-integration platforms for 5G mmWave applications
6) Illustration of techniques for RF measurement & characterization of 5G packaging materials
7) Basic antenna-in-package design considerations and techniques for 5G mmWave
Advanced Assembly Processes of Wafer Level Fan Out Packaging
Course Leader: Tom Dory, Fujifilm Electronic Materials
This PDC provides focuses on current and future assembly processes and technologies used in fan out package assembly. The objective of this PDC is to provide the students with an overview of the technologies, materials, and processes involved in the latest fan out package assembly processes.
Currently there are several choices for package assembly using fan out wafer level packages (FOWLPs). The original fan-out package; the embedded wafer-level ball-grid array (eWLB) continues to be popular. At the low cost end are low density fan out packages with <500 IOs with >8 micron L/S. At the high cost end are stacked die packages with >500 IOs and < 8 micron L/S. Multiple die can now be included in a fan out package incorporating stacked die connected using Through Silicon Vias (TSVs).
The fan out chip scale package, FOCSP, will be used as current state of the art example in the workshop. The package end user, designer and sub-cons must compare all package options on the basis of functional attributes including form factor, I/O density, performance & cost to select appropriate package from the many fan out options available.